RTL Design Engineer

Lumicity; San Francisco (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Lumicity seeks a Principal RTL Design Engineer to own the microarchitecture and RTL for next-generation memory controllers powering data centers and AI workloads.

You will lead end-to-end RTL, drive PPA improvements, and work with verification and physical design to deliver robust, production-ready designs, partnering with customers and internal teams.

Qualifications

• 10+ years of ASIC/FPGA design experience with SystemVerilog/Verilog RTL.
• Hands-on verification and scripting in Questa/Incisive/VCS, UVM, Python, Perl and TCL.
• Silicon-savvy design: synthesis, timing constraints, CDC/RDC, PPA-aware implementation.
• Bonus: high-speed interfaces and memory (AMBA AXI/CHI, HBM, LPDDR).

Responsibilities

• Own end-to-end microarchitecture and RTL for high-performance SoC blocks.
• Drive PPA optimization to ensure silicon success.
• Collaborate with verification and physical design to fix complex issues.
• Provide technical leadership from pre-sales through delivery.

Skills

ASIC/FPGA design

SystemVerilog/Verilog RTL

EE foundations

Verification & scripting

Memory interfaces (AMBA AXI/CHI, HBM,/

Tools

Questa

Incisive

VCS

UVM

Python

Perl

TCL

Job description

Data Centers, Memory Chips, AI

Role Brief:

My client is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL design of next-generation, high-performance memory controllers powering data centers and AI applications.

Responsibilities:

• Own end-to-end microarchitecture & RTL for critical, high-performance SoC blocks
• Drive PPA and silicon success through data-driven performance, power, timing, and area optimization
• Partner across verification & physical design to solve complex issues and deliver robust, production-ready designs
• Influence customer success by providing hands-on technical leadership from pre-sales through post-sales delivery

Skillset:

• 10+ years of ASIC/FPGA design expertise with deep SystemVerilog/Verilog RTL skills and a strong EE foundation.
• Hands-on verification & scripting skills across Questa/Incisive/VCS, UVM, Python, Perl, and TCL.
• Silicon-savvy design experience spanning synthesis, timing constraints, CDC/RDC, and PPA-aware implementation.
• Bonus expertise in high-speed interfaces & memory including AMBA AXI/CHI, HBM, and LPDDR—with strong communication and independent problem-solving skills.

This is an exciting opportunity to join an industry leading semiconductor company who have some of the most exciting chip/silicon IP products on the market. If you are looking for a company that will provide you with career progression and offer an excellent compensation package, then this is the job for you.

Location:

San Francisco Bay area, CA