RTL/Logic Design Engineer — High-Speed DRAM Controller

AMD; United States; On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

AMD in Santa Clara is seeking an experienced logic design engineer to contribute to the Graphics Memory Controller IP. You will craft RTL, work on HBM/GDDR interfaces, and ensure designs meet timing, power, and area targets within a fast-paced, highly collaborative environment.

Strong background in Verilog and CAD tools (Synopsys, Cadence, Mentor) is required, along with excellent communication skills and a proactive, self-starting approach to drive complex tasks to completion.

Qualifications

• Bachelor’s or Master’s degree in computer engineering, Electrical Engineering, or related field.
• Experience with RTL and Verilog for high-speed DRAM interfaces is essential.
• Proficiency with CAD tools from Synopsys, Cadence, Mentor Graphics and industry-standard verification flows.

Responsibilities

• Develop Architecture and Micro-architecture specifications for logic components.
• RTL coding and design of new blocks for HBM/GDDR DRAM technologies.
• Collaborate with Verification Engineers to ensure coverage and timing requirements.

Skills

RTL design

Verilog

High-speed interfaces

Timing analysis

Synthesis

CAD tools

Communication

Self-starting

Education

Bachelor’s or Master’s in Computer/Electrical Engineering

Tools

Synopsys

Cadence

Mentor Graphics

Job description

AMD in Santa Clara is seeking an experienced logic design engineer to contribute to the Graphics Memory Controller IP. You will craft RTL, work on HBM/GDDR interfaces, and ensure designs meet timing, power, and area targets within a fast-paced, highly collaborative environment.

Strong background in Verilog and CAD tools (Synopsys, Cadence, Mentor) is required, along with excellent communication skills and a proactive, self-starting approach to drive complex tasks to completion.