Senior TPU Design Engineer, Silicon

Socket.dev; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google Silicon is seeking a senior engineer to contribute to ML IPs and define microarchitecture for ML processors and accelerators. You’ll drive RTL development, support customers, and participate in synthesis and timing/power estimation for silicon bring-up.

The team combines cutting-edge hardware and software to deliver high-performance, power-efficient silicon solutions for Google products.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Responsibilities

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
• Drive RTL development, debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Skills

RTL design (Verilog/SystemVerilog)

IP/SoC design leadership

ARM-based SoCs

ASIC methodology

Verilog

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Job description

MINIMUM QUALIFICATIONS

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

PREFERRED QUALIFICATIONS

• Master’s degree in Electrical/Computer Engineering, or a related field.
• 10 years of experience with IP design for Complex IPs in Machine learning, Neural Processors, Multimedia or GPUs.
• Experience with methodologies for low power estimation, timing closure, and synthesis.
• Experience leading technical teams.

ABOUT THE JOB

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.

You\'ll contribute to the innovation behind products loved by millions worldwide.

Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google\'s mission is to organize the world\'s information and make it universally accessible and useful.

Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful.

We aim to make people\'s lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google

[https://www.google.com/about/careers/applications/benefits/]

RESPONSIBILITIES

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
• Drive RTL development, debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and Field-programmable Gate Array (FPGA)/silicon bring-up.