RTL Design Engineer, TPU

Socket.dev; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target 15%

Benefits

Job summary

Google's AI Hardware team is shaping the future of AI/ML hardware acceleration by driving TPU technology and custom silicon solutions. In this role, you will contribute to RTL design and verification for SoC-level components, focusing on the management and control subsystem and integration with software and system hardware.

You will work across cross-functional groups, collaborating with architecture, power, DV, and physical design teams to ensure timing, reliability, and scalable performance

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• Experience with scripting languages.
• Master's/PhD with emphasis on computer architecture is preferred.
• 8+ years of ASIC design experience.
• Strong collaboration with software and system hardware teams.
• Experience with chip management, clocking, reset, and peripherals.
• Understanding of digital design fundamentals.

Responsibilities

• Create and review management and control subsystem design microarchitectures.
• Develop SystemVerilog RTL to implement ASIC logic.
• Collaborate with architecture and power teams to evaluate features.
• Work with DV teams to create test plans and verify RTL.
• Coordinate with physical design teams to meet timing and physical requirements.

Skills

Scripting languages

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience

Master's degree or PhD in Electrical/Computer Engineering or Computer Science (emphasis on computer architecture)

Tools

SystemVerilog RTL

ASIC design

Clocking, reset, and peripherals

Digital design fundamentals

Job description

MINIMUM QUALIFICATIONS:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with scripting languages.

PREFERRED QUALIFICATIONS:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 8 years of experience in ASIC design.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

ABOUT THE JOB:

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will join a team working on SoC-level Register-Transfer Level (RTL) design for our data center accelerators. You will design RTL Intellectual Property (IP) with the focus on management and control subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., clocking, reset, error handling, debug, chip management and SOC chassis etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts. You will utilize, a background in RTL design, and the ability to lead to multi-faceted efforts involving many stakeholders.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google

https://www.google.com/about/careers/applications/benefits/.

RESPONSIBILITIES:

• Work separately to create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.