RTL Design Engineer: Power, Clocking & Reset for CPUs

Advanced Micro Devices; Fort Collins, Northern (CO, KY); Hybrid; USD 120,000 - 190,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

Advanced Micro Devices (AMD) is seeking an experienced RTL design engineer to own power management, clocking, and reset RTL for Core Complex designs. You will collaborate across Architecture, Physical Design, Verification, and Test teams to deliver high-performance fabric RTL for AMD’s next-generation cores.

The role requires strong Digital RTL Design, Verilog HDL, and scripting skills, with a track record delivering aggressive goals under tight schedules.

Qualifications

• Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Computer Science, plus experience in RTL design and microarchitecture development for processors or complex IPs.
• Strong background in Digital RTL Design, Verilog HDL, and scripting.

Responsibilities

• Collaborate with Architecture, Physical Design, Verification, and Design-for-Test teams to design, document, implement, verify, and deliver high-performance Power, Clocking, Reset, and Control Fabric RTL optimized for timing, testability, manufacturability, and physical implementation.
• Work across global IP and SoC teams to solve complex architectural interactions and drive successful product execution.
• Improve CPU design quality, performance, power, and area through innovation, simplification of design complexity, and enhanced cross-functional technical collaboration.
• Solve complex design and tool challenges using innovative approaches and communicate solutions through technical presentations to peers and management.
• Guide, mentor, and develop engineers across the organization.

Skills

RTL design

Verilog HDL

Scripting

Clocking

Power management

Microarchitecture

Education

Bachelor's or Master's in Computer Engineering/EE/CS

Tools

Verilog HDL tools

Job description

Advanced Micro Devices (AMD) is seeking an experienced RTL design engineer to own power management, clocking, and reset RTL for Core Complex designs. You will collaborate across Architecture, Physical Design, Verification, and Test teams to deliver high-performance fabric RTL for AMD’s next-generation cores.

The role requires strong Digital RTL Design, Verilog HDL, and scripting skills, with a track record delivering aggressive goals under tight schedules.