Principal CPU Core Architect - RTL & Microarchitecture

Advanced Micro Devices; Town of Fishkill (NY); On-site; USD 180,000 - 240,000; Full time

Job summary

Advanced Micro Devices (AMD) is seeking a Principal Member of Technical Staff – CPU Core Architecture/RTL Engineer in Fishkill, NY. You will craft a functional unit for AMD’s next-generation core, collaborating with experienced engineers to define high-level architecture and microarchitecture while contributing to verification, power, timing, and floorplanning efforts.

You will mentor junior engineers, lead design improvements, and drive features across RTL, synthesis, and verification domains,

Qualifications

• Bachelor’s, Master’s, or PhD with emphasis in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture.

Responsibilities

• Execute on RTL design and coding for various sections of the processor core pipeline and related logic.
• Collaborate with a team of hardware and software engineers to define the high-level architecture.
• Participate in the definition of microarchitecture of next-generation high-performance processor cores.
• Contribute to design verification, synthesis, power reduction, timing convergence, and floorplan efforts.
• Lead teams of designers collaborating on broader features, supervise the work of junior engineers, and drive methodology improvements.

Skills

Verilog RTL

Processor architecture

Logic design

RTL coding

Power optimization

Synthesis

Place & Route

Timing closure

Microarchitecture

DFT/DFD

Clocking/Reset

ISA knowledge (x86/ARM)

Perl

Shell

Tcl

Education

Electrical/CS degree

Job description

Advanced Micro Devices (AMD) is seeking a Principal Member of Technical Staff – CPU Core Architecture/RTL Engineer in Fishkill, NY. You will craft a functional unit for AMD’s next-generation core, collaborating with experienced engineers to define high-level architecture and microarchitecture while contributing to verification, power, timing, and floorplanning efforts.

You will mentor junior engineers, lead design improvements, and drive features across RTL, synthesis, and verification domains,