CPU RTL Power, Clocking, Reset Design Engineer

AMD; Fort Collins (CO); On-site; USD 120,000 - 150,000; Full time

Job summary

AMD is seeking an experienced RTL design engineer to own power management, clocking, and reset RTL for Core Complex designs within the Core Complex Cache Hierarchy team. You will collaborate across Architecture, Physical Design, Verification, and Design-for-Test groups to deliver high-performance RTL and drive next-generation cores with aggressive schedules.

The candidate should have a strong background in Digital RTL Design, Verilog HDL, and scripting, and be capable of mentoring engineers

Qualifications

• Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Computer Science.
• Strong analytical thinking and problem-solving skills; ability to guide and develop people.
• Experience delivering high-performance CPU product architecture and implementation with clocks, power, reset, and CCX interactions.

Responsibilities

• Collaborate with Architecture, Physical Design, Verification, and Design-for-Test to design, document, verify, and deliver high-performance Power, Clocking, Reset, and Control Fabric RTL.
• Work across global IP and SoC teams to solve complex architectural interactions and drive product execution.
• Improve CPU design quality, performance, power, and area through innovation and cross-functional collaboration.
• Present solutions to peers and management and mentor engineers across the organization.
• Guide, mentor, and develop engineers across the organization.

Skills

Digital RTL Design

Verilog HDL

Scripting

Education

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Computer Science

Tools

Verilog HDL

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

AMD's Core Complex Cache Hierarchy team builds the complexes that connect our compute (execution) cores — each complex combining multiple cores and their L2 caches together with a coherency fabric, optimized for the highest performance and power efficiency in the industry. Within this team, we're looking for an experienced RTL design engineer to serve as our Chip Pervasive Logic expert — owning the power management, clocking, and reset microarchitecture and RTL for these Core Complex designs. The candidate will be a key contributor to AMD's next-generation cores and Core Complexes.

The Person

The candidate has successful experience delivering aggressive goals on aggressive schedules. As a clocking and system management microarchitecture and RTL expert, it is important for the candidate to enjoy engaging with many different teams covering a breadth of technical areas. We are pushing the envelope on chip performance, power, and area, so the status quo must be challenged on every program. This environment requires creativity, innovation, and excellent verbal and written communication skills. The candidate has strong analytical thinking and problem-solving skills and enjoys using those skills to accomplish goals that many might not think possible. Our team delivers critical designs for multiple AMD products and is growing in both capability and size, so the candidate must have the ability and desire to guide and develop people.

Key Responsibilities

• Collaborate with Architecture, Physical Design, Verification, and Design-for-Test teams to design, document, implement, verify, and deliver high-performance Power, Clocking, Reset, and Control Fabric RTL optimized for timing, testability, manufacturability, and physical implementation.
• Work across global IP and SoC teams to solve complex architectural interactions and drive successful product execution.
• Improve CPU design quality, performance, power, and area through innovation, simplification of design complexity, and enhanced cross-functional technical collaboration.
• Solve complex design and tool challenges using innovative approaches and communicate solutions through technical presentations to peers and management.
• Guide, mentor, and develop engineers across the organization.

Preferred Experience

• Successful track record delivering high-performance CPU product architecture and implementation, including clocks, power management, reset, clock-domain crossing, and voltage-domain management.
• Experience with system management, voltage management and distribution, and clock control architecture, implementation, and tapeout closure.
• Experience with SoC development, either directly or through IP delivery, and collaboration across multidisciplinary engineering teams.
• Strong background in Digital RTL Design, Verilog HDL, and scripting.

Academic Credentials

• Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Computer Science, plus experience in RTL design and microarchitecture development for processors or complex IPs.

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.