High-Performance CPU Core RTL Design Engineer

Advanced Micro Devices; Austin (TX); On-site; USD 150,000 - 190,000; Full time

Job summary

Advanced Micro Devices (AMD) is hiring a CPU Core RTL Design Engineer in Austin to design and optimize high‑performance processor cores. You will work with architecture, verification, and physical design teams to develop core pipeline logic and microarchitecture features, impacting performance, power, and scalability.

Ideal candidates bring strong Verilog/SystemVerilog RTL experience in CPU/SoC/ASIC contexts, deep CPU architecture knowledge, and hands‑on scripting skills to support design flows

Qualifications

• Experience with Verilog/SystemVerilog RTL in CPU/SoC/ASIC environments.
• Strong understanding of modern CPU architecture, especially out-of-order cores.
• Expertise in logic design and high-speed processor pipelines.
• Familiarity with physical design concepts and scripts (Python/Tcl).

Responsibilities

• Design and implement RTL for CPU core pipeline components.
• Define microarchitecture features for next-generation cores.
• Collaborate with architecture, verification, and performance teams.
• Analyze and optimize performance, power, and timing.
• Support verification, synthesis, timing closure, and physical design.
• Debug pre/post-silicon issues.
• Contribute to scalable RTL methodologies.

Skills

Verilog/SystemVerilog RTL development

CPU architecture understanding

Logic design

Power optimization

DFT concepts

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering

Tools

Synthesis

Place-and-route

Timing closure

Python

Tcl

Job description

Advanced Micro Devices (AMD) is hiring a CPU Core RTL Design Engineer in Austin to design and optimize high‑performance processor cores. You will work with architecture, verification, and physical design teams to develop core pipeline logic and microarchitecture features, impacting performance, power, and scalability.

Ideal candidates bring strong Verilog/SystemVerilog RTL experience in CPU/SoC/ASIC contexts, deep CPU architecture knowledge, and hands‑on scripting skills to support design flows