Senior RTL Power Management Engineer - CPU Design

AMD; Santa Clara (CA); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

AMD is seeking an experienced microarchitect to design core clocking, reset, and power management IP for next-generation processors, located in Santa Clara, CA. You will implement RTL in Verilog/SystemVerilog, develop firmware in C/C++ for IP initialization, and work across architecture, design verification, physical design, and firmware teams.

The role requires a MS in a relevant field and 5+ years in RTL/microarchitecture, with strong debugging skills and collaboration on cross-functional

Qualifications

• MS in EE, ECE, CE, or CS with 5+ years in RTL/microarchitecture for processors or complex IP.
• Proficiency in Verilog/SystemVerilog for RTL design and verification.
• Strong C/C++ development, including embedded firmware for power management.
• Solid understanding of digital design fundamentals and low-power methodologies (clock gating, power gating, DVFS).

Responsibilities

• Design and develop microarchitecture for core clocking, reset, and power management IP.
• Collaborate with architecture, design verification, physical design, and firmware teams to integrate IP into the processor.
• Define specifications and documentation for IP microarchitecture and interfaces.
• Implement RTL in Verilog/SystemVerilog optimized for timing, area, power, and performance.
• Develop C/C++ firmware for IP initialization, configuration, and control; partner with firmware engineers.
• Perform RTL linting, CDC analysis, and related checks for design correctness.
• Work with verification to build test plans and ensure functional correctness.
• Debug RTL and firmware issues; drive cross-functional resolutions.

Skills

Verilog/SystemVerilog

RTL design

C/C++ firmware

Microarchitecture

Debugging

Clock gating/DVFS

CDC analysis

Cross-functional teamwork

Education

MS in EE/ECE/CE/CS

Job description

AMD is seeking an experienced microarchitect to design core clocking, reset, and power management IP for next-generation processors, located in Santa Clara, CA. You will implement RTL in Verilog/SystemVerilog, develop firmware in C/C++ for IP initialization, and work across architecture, design verification, physical design, and firmware teams.

The role requires a MS in a relevant field and 5+ years in RTL/microarchitecture, with strong debugging skills and collaboration on cross-functional