Principal ASIC Design Engineer

HP Enterprise; Sunnyvale (CA); Hybrid; USD 180,000 - 290,000; Full time

Benefits offered by this job

Annual equity awards

Hybrid work model

Annual bonus

Job summary

HP Enterprise in Sunnyvale, CA is seeking an experienced VLSI/ASIC architect to design and verify complex networking chip subsystems. You will write both functional and micro-architecture specifications, implement in Verilog/SystemVerilog, and drive timing and power optimizations.

You will collaborate with verification and physical design teams, lead major modules, and mentor junior engineers while maintaining high standards in performance and efficiency.

Qualifications

• Bachelor’s degree in Electrical Engineering required.
• Master’s degree strongly desired.
• 15+ years of relevant experience.
• Strong knowledge of synthesis, lint and ASIC development tools.
• Knowledge of Computer Architecture and networking protocols is highly desired.
• Excellent written and verbal communications skills.

Responsibilities

• Architect complex modules and subsystems for high performance networking chips.
• Write functional and micro-architecture specs and implement in Verilog/SystemVerilog.
• Collaborate with verification and physical design teams to meet timing and power targets.
• Lead or mentor junior engineers and interns and contribute to knowledge sharing.

Skills

Analytical thinking/problem solving

Communication skills

Leadership/mentorship

Education

BSEE (MSEE preferred)

Tools

Verilog/SystemVerilog

Synthesis/Lint tools

Perl

Python

Job description

• Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems
• Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits
• Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions
• May direct support personnel in the preparation of detailed design, design testing and prototype fabrication
• Contributions have visible technical impact on a product or major subcomponent
• Applies in-depth professional knowledge and innovative ideas to solve complex problems
• Visible contributions improve time-to-market, achieve cost reductions, or satisfy current and future unmet customer needs
• Recognized internal authority on key technology area applying innovative principles and ideas
• Provides technical leadership for significant project/program work
• Leads or participates in cross-functional initiatives and contributes to mentorship and knowledge sharing across the organization
• Architect complex modules and subsystems used in high performance networking chips
• Write detailed functional as well as the micro-architecture specification for your module with that meet the power/area/performance targets
• Implement the design using Verilog or System Verilog
• Write functional coverage/SVA to help verification catch corner case bugs
• Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases
• Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target
• Collaborate with the Verification team to make sure your block is fully validated
• Show leadership and provide guidance to new college-grad/junior engineers and interns

Benefits

• Recognition for your contributions, and potential participation in long-term incentives like annual equity awards
• A hybrid, flexible work model that ensures connectivity, a commitment to our culture and continued impact for team members
• The chance to earn an annual bonus based on performance
• Subsidized health insurance, retirement programs and paid time off, including an industry-leading maternity and paternity leave package
• Opportunities for personal and professional development to help you reach your career goals

Demonstrated skills in leading and implementing high performance subsystems from specification to final netlistKnowledge of synthesis/lint and other tools used in typical ASIC development process is highly desiredStrong analytical/ problem solving skillsBachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 15+ years of relevant experienceKnowledge of Perl/Python is strongly desiredStrong coding skills in Verilog/System Verilog through previous work experience are necessaryKnowledge of Computer Architecture/networking protocols through prior work is strongly desiredExcellent written and verbal communications skills is necessary