RTL Design Engineer

Broadcom; Chandler (AZ); On-site; USD 127,100 - 203,400; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(K) participation with company matching

Employee Stock Purchase Program

Paid sick leave and vacation time

Job summary

A leading semiconductor company in Chandler, Arizona, is seeking an experienced digital designer for analog mixed signal IP and IO design. You will define architecture, develop verification strategies, and collaborate across teams. Ideal candidates have a Master's degree and over 10 years of relevant experience in digital implementation and timing analysis. The role features a competitive salary and comprehensive benefits package, including medical and 401(K) matching.

Qualifications

• 10+ years of relevant industry experience.
• Deep understanding of timing analysis with PrimeTime flow.
• Experience with advanced FinFET process nodes.

Responsibilities

• Define digital architecture and verification strategies.
• Design and verify Verilog/SystemVerilog RTL.
• Drive comprehensive test plans to ensure quality of design.

Skills

Digital implementation flow

Timing analysis

Verilog/SystemVerilog

Problem solving

Scripting in Perl, Python and Tcl

Education

MS degree

Tools

Synopsys Formality

Cadence Conformal

Tessent

Job description

Job Description

Broadcom’s Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading‑edge AI programs on advanced nodes. Joining a world‑class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.

Responsibilities

• Define the digital architecture and verification strategies for complex AMS and IO subsystems
• Design, synthesis, and verification of Verilog/SystemVerilog RTL
• Analysis, debug, and resolution of Lint and CDC issues in the design
• Design convergence to timing closure utilizing RTL optimization strategies
• Conduct formal verification of design with Synopsys Formality / Cadence Conformal
• Generate timing constraints for synthesis and STA at the block‑level and SoC top‑level
• Drive comprehensive test plans to ensure quality of design
• Collaborate with cross‑functional teams, ranging from analog/mixed‑signal circuit designers to SoC‑level system integration
• Create and maintain detailed specification, design, and verification documentation

Job Requirements

• MS +10 years of relevant industry experience
• Experience with digital implementation flow from RTL synthesis to timing closure
• Deep understanding of timing analysis with PrimeTime flow and generation of Liberty models
• Experience with Tessent tool for DFT insertion and verification
• Proficient with Perl, Python and Tcl scripting
• Strong problem solving skills with attention to detail
• Must be self‑motivated and able to work effectively across internal and external engineering teams

Highly Desired Qualifications

• Solid understanding of transistor‑level circuit behavior
• Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation
• Experience with advanced FinFET process nodes, including features, technology limitations and PPA tradeoffs

Compensation and Benefits

The annual base salary range for this position is $127,100 - $203,400.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program, Employee Assistance Program, company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Equal Employment Opportunity

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.