Lead ASIC Design Engineer

Broadcom; San Jose (CA); On-site; USD 143,800 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Competitive equity grants

Comprehensive benefits package

Job summary

Broadcom is seeking a Principal Digital Design Engineer in San Jose, CA, to serve as the Chip Lead for innovative silicon projects. This role involves defining architecture, guiding design integration, and mentoring junior engineers throughout the engineering process.

The ideal candidate should possess over 12 years of experience in digital design, expertise in SystemVerilog/Verilog, and a strong understanding of front-end EDA tools. An impressive benefits package is offered, along with a competitive salary.

Qualifications

• 12+ years of experience in ASIC/SoC digital design with proven chip project ownership.
• Expert in SystemVerilog/Verilog and microarchitecture principles.
• Experience with front-end EDA tools for synthesis, STA, and CDC analysis.

Responsibilities

• Define top-level digital architecture and manage integration lifecycle.
• Drive logic synthesis and static timing analysis for chip design.
• Collaborate with teams during silicon validation and chip bring-up.

Skills

SystemVerilog/Verilog digital logic design

Team leadership

Cross-disciplinary alignment

Documentation skills

Communication skills

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

Design Compiler

PrimeTime

SpyGlass

Job description

Job Description

We are seeking a hands‑on Principal Digital Design Engineer to serve as the Chip Lead for our next‑generation silicon projects. In this high‑impact role, you will be the primary technical anchor responsible for the top‑level architecture, microarchitecture, and full chip integration. You will guide a cross‑disciplinary team spanning analog design, physical design, and verification, owning the design outcome end‑to‑end from early product definition to a successful foundry tape‑out.

Leadership & Strategic Responsibilities

• Technical Ownership: Serve as the central Chip Lead, defining top‑level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.
• Cross‑Discipline Alignment: Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.
• Tape‑Out Delivery: Own and drive the final tape‑out sign‑off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.
• Mentorship & Culture: Provide technical guidance, code reviews, and architectural mentorship to mid‑level and junior engineers on the team.

Technical Execution Responsibilities

• RTL Design: Author, optimize, and maintain high‑quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).
• Timing & Constraint Ownership: Drive top‑level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block‑level timing budgets for the PD team.
• Front‑End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), static timing analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
• IP Management: Manage the integration of custom internal analog macros, mixed‑signal blocks, and third‑party soft/hard IP.
• Silicon Validation: Collaborate with post‑silicon validation and software teams during initial chip bring‑up and lab debug phases.

Required Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
• RTL Mastery: Expert‑level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
• Tool Fluency: Deep experience with front‑end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
• Silicon Track Record: Must have a proven history of successful, first‑pass silicon tape‑outs on modern process technologies.
• Communication: Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project.
• Work Authorization: Must have legal authorization to work in the US.

Preferred & Bonus Skills

• Experience with mixed‑signal or high‑speed PHY‑adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects).
• Familiarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan.
• Proficiency in scripting (Python, Tcl, Perl) to automate and streamline front‑end design flows.

Compensation & Benefits

The annual base salary range for this position is $143,800 - $230,000.

As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive a competitive new hire equity grant, as well as annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.

Broadcom offers a comprehensive benefits package: medical, dental, and vision plans; 401(k) participation with company matching; Employee Stock Purchase Program (ESPP); Employee Assistance Program (EAP); company paid holidays; paid sick leave and vacation time; and compliance with all applicable laws for paid family leave and other leaves of absence.

Broadcom is proud to be an equal‑opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.