R&D Engineer IC Design 4

Broadcom Inc.; Austin (TX); On-site; USD 121,900 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

company paid holidays

paid sick leave and vacation time

Job summary

Broadcom Inc. in Austin, TX seeks a front end ASIC design engineer responsible for design blocks for cores, including architecture, logic design, synthesis, and verification. You will perform timing analysis and formal verification, simulate with Verilog, and ensure the ASIC flow from RTL to timing closure.

The role requires 8+ years (or 6+ with MS) and BS/MS in Electrical or Computer Engineering. occassional travel may be required; equity and bonuses are part of the package.

Qualifications

• BS/MS in Electrical or Computer Engineering or equivalent
• 8+ years of related experience; or Masters with 6+ years
• Experience with complete ASIC/standard product flow from RTL synthesis to timing closure
• Proficiency with TCL/Perl scripting, Synthesis tools, Primetime timing analysis, Liberty LIB models, Formal verification, Spyglass, Power analysis, DFT/scan, and version control

Responsibilities

• Front end design and verification of design blocks for the cores
• Architecture definition, logic design, synthesis, constraint development
• Verification through simulation and formal methods; timing analysis from physical implementation
• Design blocks from system requirements and simulate/debug with Verilog
• Familiarity with full ASIC design and implementation flow

Skills

RTL synthesis

Timing analysis

Formal verification

DFT / scan

Power analysis

Liberty LIB models

Verilog simulation

Version control

TCL/Perl scripting

Scripting / EDA

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Design Compiler

RTL Compiler

Primetime

Liberty LIB models

Formality

Conformal

Spyglass

svn/git

Power analysis

Job description

Job Description

You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow.

• Ability to work independently as well as part of a large team spanning multiple geographies.
• Education: BS/MS in Electrical or Computer Engineering or equivalent
• Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience
• Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.
• Requires proficiency with the following design tools / flows:
  • TCL/Perl scripting
  • Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler
  • Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries
  • Understanding of liberty LIB models for timing
  • Formal verification (Synopsys Formality / Cadence Conformal)
  • Spyglass Lint
  • Power analysis of RTL and gate level netlists
  • Familiarity with DFT (design for test) and scan methodology
  • Version control (svn, git, etc)

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time

The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Equal Opportunity and Diversity Statement

Broadcom is proud to be an equal opportunity employer.

We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.

We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Additional Information

Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

For more information please visit our video library and check out our Connected by Broadcom series.

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