R&D Engineer IC Design 4

Broadcom Inc.; San Jose (CA); On-site; USD 121,900 - 195,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(K) participation with company matching

Employee Stock Purchase Program (ESPP)

Paid sick leave and vacation time

Discretionary annual bonus

Job summary

Broadcom Inc. is looking for a skilled professional for a front-end design and verification role specializing in ASIC design blocks. The ideal candidate will handle architecture definition, design verification through simulation, and logic design. A Bachelor's degree with significant experience or a Master's with lesser experience is required.

The position offers a competitive salary along with a comprehensive benefits package including medical, dental, and equity awards. Immediate eligibility for a discretionary annual bonus is also included.

Qualifications

• 8+ years of related experience for Bachelor's or 6+ years for Master's.
• Familiarity with complete ASIC design and implementation flow.
• Experience in design verification through simulation and formal verification.

Responsibilities

• Front-end design and verification of ASIC design blocks.
• Architecture definition and logic design.
• Simulation and debugging of designs.

Skills

Independent and team-oriented work

Verilog simulation

TCL/Perl scripting

Timing analysis

Formal verification

Power analysis

Version control (svn, git)

Education

B.S./M.S. in Electrical or Computer Engineering

Tools

Synopsys Design Compiler

Cadence RTL compiler

Primetime

Synopsys Formality

Cadence Conformal

Spyglass Lint

Job description

You will be responsible for the front‑end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation.

You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow.

Key Responsibilities

• Ability to work independently as well as part of a large team spanning multiple geographies.

Education and Experience

• B.S./M.S. in Electrical or Computer Engineering or equivalent.
• Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience.
• Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.

Required Tools and Flows

• TCL/Perl scripting.
• Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler.
• Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries.
• Understanding of liberty LIB models for timing.
• Formal verification (Synopsys Formality / Cadence Conformal).
• Spyglass Lint.
• Power analysis of RTL and gate level netlists.
• Familiarity with DFT (design for test) and scan methodology.
• Version control (svn, git, etc).

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 – USD 195,000.00. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive a competitive new hire equity grant, as well as annual equity awards.

Broadcom offers a comprehensive benefits package that includes medical, dental, and vision plans; 401(K) participation with company matching; Employee Stock Purchase Program (ESPP); Employee Assistance Program (EAP); company paid holidays; paid sick leave and vacation time; and compliance with all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.