RL Research Engineer - Chip Design & AI Acceleration

Anysilicon; San Francisco (CA); Hybride; USD 180 000 - 240 000; Plein temps

Résumé du poste

Anthropic in San Francisco, CA is seeking a Research Engineer to advance AI hardware for RL and silicon design, with a hybrid work model. You will invent RL environments for RTL generation and verification, optimize EDA tool latency, run experiments, and shape the research roadmap while collaborating with researchers and engineers across the company to deliver production-ready results.

Experience in ASIC/FPGA design, RTL verification, and familiarity with ML accelerators will be valued as you

Qualifications

• Expertise in ASIC or FPGA design, including RTL and design verification.
• Experience with EDA tools and processes.
• Chip design experience from spec to silicon.
• Ability to balance research and engineering.
• Passion for AI and safe systems.

Responsabilités

• Invent, design, and implement RL environments for RTL generation and verification.
• Work on EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape the research roadmap.
• Deliver work into research and production training runs.
• Collaborate with researchers and engineers across Anthropic.

Connaissances

ASIC/FPGA design

RTL verification

EDA tools

Chip design

ML accelerators

Description du poste

Anthropic in San Francisco, CA is seeking a Research Engineer to advance AI hardware for RL and silicon design, with a hybrid work model. You will invent RL environments for RTL generation and verification, optimize EDA tool latency, run experiments, and shape the research roadmap while collaborating with researchers and engineers across the company to deliver production-ready results.

Experience in ASIC/FPGA design, RTL verification, and familiarity with ML accelerators will be valued as you