Research Engineer, Chip Design RL [Reinforcement Learning]

Anysilicon; San Francisco (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Anthropic in San Francisco, CA is seeking a Research Engineer to advance AI hardware for RL and silicon design, with a hybrid work model. You will invent RL environments for RTL generation and verification, optimize EDA tool latency, run experiments, and shape the research roadmap while collaborating with researchers and engineers across the company to deliver production-ready results.

Experience in ASIC/FPGA design, RTL verification, and familiarity with ML accelerators will be valued as you

Qualifications

• Expertise in ASIC or FPGA design, including RTL and design verification.
• Experience with EDA tools and processes.
• Chip design experience from spec to silicon.
• Ability to balance research and engineering.
• Passion for AI and safe systems.

Responsibilities

• Invent, design, and implement RL environments for RTL generation and verification.
• Work on EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape the research roadmap.
• Deliver work into research and production training runs.
• Collaborate with researchers and engineers across Anthropic.

Skills

ASIC/FPGA design

RTL verification

EDA tools

Chip design

ML accelerators

Job description

Anthropic, San Francisco, CA Hybrid work

Job Description:

Anthropic is dedicated to creating reliable, interpretable, and steerable AI systems that are safe and beneficial for users and society. The company is expanding its team of researchers, engineers, policy experts, and business leaders to advance AI technology. The Reinforcement Learning (RL) teams play a crucial role in this mission, contributing to the development of Claude models and focusing on areas such as effective computer usage, code generation, RL research for large language models, scalable infrastructure, and enhanced reasoning capabilities. The Code RL team is specifically looking for a Research Engineer to improve models' abilities in hardware design, particularly in silicon design.

Responsibilities:

• Invent, design, and implement RL environments for RTL generation and verification.
• Work on EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape the research roadmap.
• Deliver work into research and production training runs.
• Collaborate with researchers and engineers across Anthropic.

Qualifications:

• Expertise in ASIC or FPGA design, including RTL and design verification.
• Fluency with industry EDA tools and processes.
• Experience in chip design from specification to silicon.
• Ability to balance research exploration with engineering implementation.
• Passion for AI and commitment to developing safe systems.

Skills:

• Experience with reinforcement learning and evaluations.
• Familiarity with chip design automation tools.
• Background in ML accelerators or high-performance compute hardware.
• Knowledge of high-level synthesis or architecture simulators.