AI-Driven Chip Design Software Engineer

OpenAI; San Francisco (CA); On-site; USD 266,000 - 468,000; Full time

Job summary

OpenAI in San Francisco is seeking a Software Engineer to build the research infrastructure and tooling that helps OpenAI models design silicon.

You will work across reinforcement learning environments, RTL generation, verification, and tool integration to enable researchers to run experiments and iterate on new ideas.

We value strong coding fundamentals, practical tradeoffs, and the ability to learn chip-design concepts alongside hardware experts.

Qualifications

• Strong software engineering fundamentals with designing, implementing and debugging reliable systems.
• Ability to work across a stack and make practical tradeoffs between speed and correctness.
• Experience delivering substantial software projects and explaining technical decisions.

Responsibilities

• Build and maintain infrastructure for reinforcement learning environments, evaluations, and long-running experiments.
• Integrate EDA tools into RTL generation, verification, and physical design workflows.
• Improve experiment reliability, reproducibility, observability, and performance.
• Develop tooling and model harnesses for rapid testing of ideas with measurable metrics.
• Collaborate with researchers and engineers to turn experiments into reusable systems and training workflows.
• Own ambiguous projects end to end and communicate progress.

Skills

Software engineering fundamentals

Debugging reliable systems

Cross-stack collaboration

Independently deliver projects

Tools

Python

Containerized tools

Verilog/SystemVerilog

EDA tools

Job description

OpenAI in San Francisco is seeking a Software Engineer to build the research infrastructure and tooling that helps OpenAI models design silicon.

You will work across reinforcement learning environments, RTL generation, verification, and tool integration to enable researchers to run experiments and iterate on new ideas.

We value strong coding fundamentals, practical tradeoffs, and the ability to learn chip-design concepts alongside hardware experts.