RL Research Engineer: ASIC/FPGA RTL & Design

Anthropic; New York (NY); Hybrid; USD 500,000 - 850,000; Full time

Benefits offered by this job

Equity donation matching

Generous vacation

Parental leave

Flexible working hours

Office space in multiple US offices

Job summary

Anthropic seeks a Research Engineer to advance our models’ ability to design silicon, turning chip design expertise into model learning signals. You will invent and implement RL environments for RTL generation, verification, and physical design optimization, while addressing EDA latency and proxy rewards.

Strong candidates have ASIC/FPGA experience, RTL design expertise, and a track record of taking chips from spec to silicon within hybrid-remote environments.

Qualifications

• Experience in ASIC/FPGA design and RTL verification.
• Proficiency with industry EDA tools and methodologies.
• Experience taking chips from spec to silicon.
• Ability to balance research exploration with engineering delivery.

Responsibilities

• Invent, design, and implement RL environments and evaluations for agentic RTL generation, design verification, and physical design optimization.
• Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape our roadmap.
• Deliver work into research and production training runs.
• Collaborate with researchers and engineers across and outside Anthropic.

Skills

ASIC or FPGA design

RTL

Formal methods

EDA tools

Tape-out experience

Education

Bachelor's degree in a relevant field

Tools

UVM

DFT

Place-and-route

Timing closure

Synthesis

Job description

Anthropic seeks a Research Engineer to advance our models’ ability to design silicon, turning chip design expertise into model learning signals. You will invent and implement RL environments for RTL generation, verification, and physical design optimization, while addressing EDA latency and proxy rewards.

Strong candidates have ASIC/FPGA experience, RTL design expertise, and a track record of taking chips from spec to silicon within hybrid-remote environments.