Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic

San Francisco (CA)

Hybrid

USD 500,000 - 850,000

Full time

14 days+

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Benefits offered by this job

Flexible hours
Generous vacation
Parental leave
Equity donation matching
Supportive office environment

Job summary

Anthropic's RL team is hiring a Research Engineer to advance silicon design for Claude models. You will design RL environments, perform RTL verification, and optimize physical design flows across ASIC/FPGA toolchains as part of a cross‑functional research and production loop.

Collaborate with researchers and engineers to ship scalable RL tools, contribute to ML accelerators and high‑performance compute hardware, and help shape the team's roadmap and impact.

Qualifications

  • Bachelor’s degree or equivalent combination of education, training, and/or experience.
  • Experience with RTL design verification and ASIC/FPGA flows is required.
  • Fluency with industry EDA tools and processes.

Responsibilities

  • Invent, design, and implement RL environments and evaluations for agentic RTL generation and physical design optimization.
  • Work on cross‑cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
  • Conduct experiments and shape our roadmap.
  • Deliver work into research and production training runs.
  • Collaborate with other researchers and engineers across and outside Anthropic.

Skills

ASIC/FPGA design RTL
RTL verification
PPA optimization
DFT
ECOs

Education

Bachelor’s degree or equivalent
Field relevant to role

Tools

EDA tools

Job description

About Anthropic

Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems.

About the RL Teams

Our Reinforcement Learning teams lead Anthropic's reinforcement learning research and development and play a critical role in advancing our AI systems. We have contributed to all Claude models, with significant impacts on the autonomy and coding capabilities of Claude Fable 5 and Opus 4.8. Our work spans several key areas:

  • Developing systems that enable models to use computers effectively
  • Advancing code generation through reinforcement learning
  • Pioneering fundamental RL research for large language models
  • Building scalable RL infrastructure and training methodologies
  • Enhancing model reasoning capabilities
About the Role

We’re hiring for the Code RL team within the RL organization. As a Research Engineer, you’ll advance our models’ ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at.

Responsibilities
  • Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, and physical design optimization.
  • Work on cross‑cutting RL considerations such as EDA‑tool latency optimization and proxy rewards.
  • Conduct experiments and shape our roadmap.
  • Deliver your work into research and production training runs.
  • Collaborate with other researchers and engineers across and outside Anthropic.
Qualifications
  • Expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage‑driven), physical design (synthesis, place‑and‑route, timing closure), PPA optimization, DFT, ECOs.
  • Fluency with industry EDA tools and processes.
  • Experience tapping out chips and going from spec to silicon.
  • Ability to balance research exploration with engineering implementation.
  • Passion for AI’s potential and commitment to developing safe and beneficial systems.
Additional Qualifications for Strong Candidates
  • Experience with reinforcement learning, evaluations, or environments.
  • Built tooling or automation around chip design flows.
  • Worked on ML accelerators or high‑performance compute hardware.
  • Familiarity with high‑level synthesis or architecture simulators.
Annual Salary

$500,000—$850,000 USD

Logistics

Minimum Education: Bachelor’s degree or equivalent combination of education, training, and/or experience.
Required Field of Study: A field relevant to the role as demonstrated through coursework, training, or professional experience.
Minimum Years of Experience: Minimum years of experience correlate with the internal job level requirements.
Location-based Hybrid Policy: All staff are expected to be in one of our offices at least 25% of the time. Some roles may require more time in our offices.
Visa Sponsorship: We sponsor visas when possible and make reasonable efforts to assist with visa acquisition if an offer is made.

Compensation & Benefits

Competitive compensation and benefits, including flexible working hours, generous vacation and parental leave, optional equity donation matching, and a supportive office environment.

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