RISC-V Linux Kernel Architect - High-Core Server Systems

SiFive; Arizona; On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Healthcare benefits

Retirement plans

Paid time off

Job summary

SiFive, the world leader in RISC-V, seeks an experienced Linux kernel software architect. You will improve and debug the RISC-V Linux kernel for high-core-count servers, engaging with upstream communities and patching on public mailing lists.

You’ll work with system software, validation teams, and hardware engineers to refine core designs. In this role you will collaborate across SiFive and RISC-V International to solve challenging issues on emulation platforms and FPGA deployments, contributing

Qualifications

• Must have experience working on concurrency-sensitive code in the upstream Linux kernel and a track record of writing and reviewing patches on public mailing lists.
• Experience debugging challenging software and hardware bugs in CPUs and SoCs.
• Experience working with CPU architects and RTL engineers.
• Experience developing and debugging Linux on FPGA and emulation platforms.
• Experience with hypervisors and virtualization.
• Familiarity with the RISC-V architecture.

Responsibilities

• Improve and debug the RISC-V Linux kernel, with a focus on high core count server systems.
• Interact with the upstream Linux and OpenSBI communities, posting and reviewing patches.
• Collaborate with system software and system validation teams and with hardware engineers to improve core and system designs.

Skills

Concurrency in Linux kernel

Patching upstream Linux kernel

Debugging CPU/SoC bugs

RISC-V familiarity

Hardware collaboration

Virtualization

Tools

OpenSBI

Emulation platforms

Devicetree

UEFI

Rust

Job description

SiFive, the world leader in RISC-V, seeks an experienced Linux kernel software architect. You will improve and debug the RISC-V Linux kernel for high-core-count servers, engaging with upstream communities and patching on public mailing lists.

You’ll work with system software, validation teams, and hardware engineers to refine core designs. In this role you will collaborate across SiFive and RISC-V International to solve challenging issues on emulation platforms and FPGA deployments, contributing