Design Verification Engineer

IC Resources; United States; Remote; USD 110,000 - 150,000; Full time

Job summary

IC Resources is seeking Design Verification Engineers for contract, W2 roles in the United States to support tapeout of high‑speed interconnect chips. You will build and extend UVM testbenches, write test plans and sequences, and drive regressions to closure before fab.

Ideal candidates have 5+ years of DV experience with SystemVerilog/UVM, ownership of a block or subsystem through tapeout, and strong debugging skills. Familiarity with PCIe, Ethernet or DDR is a plus.

Qualifications

• 5+ years of DV experience with SystemVerilog and UVM.
• At least one tapeout where you owned a block or subsystem through to closure.
• Strong debugging instincts and ability to work to a fixed date.

Responsibilities

• Build and extend UVM testbenches at block and subsystem level.
• Write test plans, sequences, checkers and functional coverage.
• Run regressions, debug failures and collaborate with designers to close bugs.
• Drive code and functional coverage to signoff targets.
• Support gate level sims and final checks ahead of tapeout.

Skills

DV with SystemVerilog/UVM

Tapeout ownership

Debugging under fixed dates

PCIe/Ethernet/DDR/AMBA/AXI familiarity

Python/TCL scripting

Job description

Design Verification Engineers | Contract, W2 | Tapeout Support

We’re working with a semiconductor company building the high speed interconnect chips that link AI accelerators in the data center. They are heading into tapeout and need more DV firepower to get there.

There are multiple contract roles available for an initial 12 month duration.

The architecture is set and the RTL is maturing. The job now is coverage closure, regressions and bug hunting, so the chip works when it goes to the fab.

What you’ll be doing

• Building and extending UVM testbenches at block and subsystem level
• Writing test plans, sequences, checkers and functional coverage
• Running regressions, debugging failures and working with designers to close bugs fast
• Driving code and functional coverage to signoff targets
• Supporting gate level sims and final checks in the run up to tapeout

What we’re looking for

• 5+ years in DV with SystemVerilog and UVM
• At least one tapeout where you owned a block or subsystem through to closure
• Strong debug instincts and comfort working to a fixed date
• Experience with PCIe, Ethernet, DDR, AMBA/AXI or SoC level integration is a plus
• Formal, emulation or Python scripting is a bonus, not a requirement

No C2C and no third parties.

Remote

Must be authorized to work in the US, without sponsorship