Remote DFT Engineer — Holographic Chip Design (3‑Month)

Swave; United States; Remote; USD 127,000 - 191,000; Part time

Job summary

Swave Photonics seeks a DFT Engineer for a critical, fixed‑term assignment. The role is fully remote with the HQ in Leuven, duration 3 months, immediate start as a freelance/contract engagement.

You will lead DFT strategy, pattern generation, and diagnostic testing across digital blocks to enable efficient silicon bring‑up. Ideal candidates have 5+ years in DFT, ATPG/scan insertion, and experience with Cadence Modus or Tessent.

Qualifications

• 5+ years of hands-on experience in DFT architecture, scan insertion, and ATPG for advanced semiconductor designs.
• English language proficiency (written and spoken) is mandatory.

Responsibilities

• Build and own the DFT flow: tool selection, configuration, and flow setup.
• DFT implementation: insertion, architecture, and strategy across digital blocks for maximum test coverage (ATPG, JTAG/Boundary Scan).
• Methodology and flow optimization: advise design teams to improve synthesis flows and constraints.
• Diagnostics and test execution: generate/validate test sets, fault grading, and test strategies for silicon bring‑up.

Skills

DFT strategy

ATPG planning

Test pattern creation

English fluency

Tools

Cadence Modus

Tessent

Job description

Swave Photonics seeks a DFT Engineer for a critical, fixed‑term assignment. The role is fully remote with the HQ in Leuven, duration 3 months, immediate start as a freelance/contract engagement.

You will lead DFT strategy, pattern generation, and diagnostic testing across digital blocks to enable efficient silicon bring‑up. Ideal candidates have 5+ years in DFT, ATPG/scan insertion, and experience with Cadence Modus or Tessent.