R&D Engineer IC Design 4

Anysilicon; Austin, Northern (TX, KY); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Broadcom is seeking a highly skilled engineer for front-end design and verification of ASIC cores. You will define architecture, implement logic, and drive synthesis with constraints, while performing rigorous verification through simulation and formal methods.

The role requires strong timing analysis capabilities, FPGA/RTL familiarity, and experience with SDC constraints, Verilog, and related tools. You will collaborate with cross-functional teams to meet aggressive timing and quality goals in

Qualifications

• BS/MS in Electrical or Computer Engineering or equivalent.
• 8+ years experience for BS, or 6+ years with MS.

Responsibilities

• Define architecture and design logic blocks based on system requirements.
• Conduct synthesis and develop constraints for design blocks.
• Perform design verification through simulation and formal verification methods.
• Analyze timing from physical implementation and ensure timing closure.
• Simulate and debug designs using Verilog simulation.

Skills

TCL/Perl scripting

Synthesis tooling

Timing analysis

Formal verification

DFT/scan

Version control

Verilog/VHDL

Liberty timing models

Education

BS/MS in Electrical or Computer Engineering

Tools

Synopsys Design Compiler/DC topo

Cadence RTL compiler

Primetime

Liberty LIB models

Synopsys Formality

Cadence Conformal

Spyglass Lint

Job description

Broadcom is seeking a skilled engineer for front-end design and verification of ASIC cores. The role involves architecture definition, logic design, synthesis, and design verification through simulation and formal methods. Candidates should have a strong background in ASIC design and implementation, with the ability to work independently and collaboratively across teams.

Responsibilities:

• Define architecture and design logic blocks based on system requirements.
• Conduct synthesis and develop constraints for design blocks.
• Perform design verification through simulation and formal verification methods.
• Analyze timing from physical implementation and ensure timing closure.
• Simulate and debug designs using Verilog simulation.

Qualifications:

• BS/MS in Electrical or Computer Engineering or equivalent.
• Bachelor's degree with 8+ years of related experience, or a Master's degree with 6+ years of related experience.

Skills:

• Proficiency in TCL/Perl scripting.
• Experience with Synopsys Design Compiler/DC topo or Cadence RTL compiler for synthesis.
• Timing analysis experience with Primetime for high frequency designs.
• Understanding of liberty LIB models for timing analysis.
• Experience with formal verification tools like Synopsys Formality or Cadence Conformal.
• Familiarity with Spyglass Lint and power analysis of RTL and gate level netlists.
• Knowledge of DFT (design for test) and scan methodology.
• Version control experience with tools like SVN or Git.

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