Principal Verification Engineer - UVM for AI Processor

Thrive Recruitment Agency; Sunnyvale (CA); On-site; USD 110,000 - 140,000; Full time

Job summary

A leading recruitment firm is seeking a skilled Verification Design Engineer (Mid/Sr/Princ) in Sunnyvale, California. The role involves creating UVM testbench environments for a custom AI processor, ensuring proper functionality through developed infrastructure and collaboration with design teams. Candidates should possess at least 3 years of experience with UVM testbenches, knowledge of System Verilog, and proficiency in Python. This position offers a dynamic environment focused on innovative architecture and verification methodologies.

Qualifications

• 3+ years of experience with UVM Testbench Infrastructure.
• In-depth knowledge of UVM testbenches and testing.
• Experience with random testbench implementation and functional coverage.

Responsibilities

• Create UVM testbench environment interfacing with Digital AMS and software.
• Develop tests and coverage to ensure functionality.
• Collaborate with design teams to develop test plans.

Skills

UVM Testbench Infrastructure

System Verilog

Python

C/C++

Technical leadership

Team collaboration

Education

BSEE +4 years relevant experience

MSEE preferred

Tools

Jenkins

git

JIRA

Job description

A leading recruitment firm is seeking a skilled Verification Design Engineer (Mid/Sr/Princ) in Sunnyvale, California. The role involves creating UVM testbench environments for a custom AI processor, ensuring proper functionality through developed infrastructure and collaboration with design teams. Candidates should possess at least 3 years of experience with UVM testbenches, knowledge of System Verilog, and proficiency in Python. This position offers a dynamic environment focused on innovative architecture and verification methodologies.