(Mid/Sr/Princ) Verification Design Engineer (UVM)

Thrive Recruitment Agency; Sunnyvale (CA); On-site; USD 110,000 - 140,000; Full time

Job summary

A leading recruitment firm is seeking a skilled Verification Design Engineer (Mid/Sr/Princ) in Sunnyvale, California. The role involves creating UVM testbench environments for a custom AI processor, ensuring proper functionality through developed infrastructure and collaboration with design teams. Candidates should possess at least 3 years of experience with UVM testbenches, knowledge of System Verilog, and proficiency in Python. This position offers a dynamic environment focused on innovative architecture and verification methodologies.

Qualifications

• 3+ years of experience with UVM Testbench Infrastructure.
• In-depth knowledge of UVM testbenches and testing.
• Experience with random testbench implementation and functional coverage.

Responsibilities

• Create UVM testbench environment interfacing with Digital AMS and software.
• Develop tests and coverage to ensure functionality.
• Collaborate with design teams to develop test plans.

Skills

UVM Testbench Infrastructure

System Verilog

Python

C/C++

Technical leadership

Team collaboration

Education

BSEE +4 years relevant experience

MSEE preferred

Tools

Jenkins

git

JIRA

Job description

Job Openings (Mid/Sr/Princ) Verification Design Engineer (UVM)

About the job (Mid/Sr/Princ) Verification Design Engineer (UVM)

In this role, you will be driving the verification effort and methodology while working closely with architects, designers, and ML software engineers. You will be creating a UVM testbench environment for a custom AI processor, including testbenches, tests, regressions, and functional coverage to achieve zero bug escapes. The UVM environment will co-exist with AMS testbenches to provide strong verification of the novel Celestial AI architecture that enables higher scalable performance than traditional designs. The extended environment you create will be used to cover iterative and fast-paced HLS-generated code.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Create UVM testbench Environment, interfacing with Digital AMS and Software
• Develop infrastructure, testbenches, tests, and coverage to ensure proper functionality
• Collaborate with ASIC and software design teams to develop testplans
• Design, develop, and maintain modular and reusable UVM testbenches for Celestial ML custom blocks.
• Confirm test completeness through code and functional coverage
• Provide technical leadership and mentoring

QUALIFICATIONS:

• Requires 3+ years of experience with UVM Testbench Infrastructure
• In depth knowledge of UVM testbenches, stimulus, constraints, and testing
• Extensive experience with System Verilog, Python, and some experience with C/C++
• Experienced with random testbench implementation, code and functional coverage
• Self-motivated with strong technical skills, as well as a great team player and effective communicator
• Prefer extensive knowledge of Python test infrastructure integrating Jenkins, git, JIRA
• Experience with PCIE, AXI-4, ARM standards beneficial
• Experience with formal verification preferred.
• History of high quality first silicon success
• Some knowledge of ML, AI trends, and HW accelerator landscape, preferred.
• BSEE +4 years relevant experience. MSEE preferred.