AI - UVM Verification Engineer in United

Energy Jobline ZR; United (WV); Remote; USD 90,000 - 130,000; Full time

Job summary

Paradigm Works, Inc. is seeking a full-time remote UVM Verification Engineer to develop and maintain SystemVerilog/UVM testbenches for complex RTL designs. You will create test plans, execute tests, debug failures, and collaborate with design, validation, and architecture teams to ensure coverage and correctness.

The role emphasizes mentoring, continuous improvement of verification methodologies, and exposure to AI-assisted verification techniques in a distributed, remote setting.

Qualifications

• Strong RTL design and functional verification skills with SystemVerilog and UVM.
• Familiarity with AI for verification is a plus and an eagerness to learn AI-based verification methods.
• Experience with EDA tools, simulators, waveform viewers, and version control.
• Excellent communication in a distributed remote team.

Responsibilities

• Develop and maintain SystemVerilog/UVM testbenches, including stimulus, checkers, monitors, and scoreboards.
• Create test plans, write and execute tests, and debug simulation failures.
• Collaborate with design, validation and architecture teams to achieve coverage goals.
• Analyze verification results, track defects, and refine verification environments.
• Mentor teammates and participate in technical discussions with clients when needed.

Skills

AI for verification

RTL design

SystemVerilog

UVM

Debugging

EDA tools

Version control

Python scripting

Education

Bachelor’s or Master’s degree in Electrical Engineering / Computer Engineering / Computer Science

Tools

SystemVerilog/UVM tools

Job description

Job Description

Company Description

Paradigm Works, Inc. delivers world-class chip development services, software and training (Sunburst Design) for digital integrated circuits, with a strong focus on innovation, technical excellence, and customer service. The company is a pioneer in verification and design services, custom enabling IP, and training for chip development. Paradigm Works partners with clients across major global markets, supporting complex projects and advanced semiconductor designs. Its consulting expertise spans AI driven Architecture, Design, Synthesis, Functional Verification, Timing Closure, Test, and Physical Design, offering comprehensive end-to-end support for chip development teams.

Role Description

This is a full-time remote role for a UVM Verification Engineer. Using leading AI tools, the UVM Verification Engineer will develop and maintain SystemVerilog/UVM testbenches, including stimulus , checkers, monitors, and scoreboards to verify complex RTL designs. Responsibilities include creating test plans, writing and executing tests, debugging simulation failures, and collaborating closely with design, validation, and architecture teams to ensure functional correctness and coverage goals. The engineer will analyze verification results, track defects, refine test environments, and contribute to continuous improvement of verification methodologies and automation. The role may also involve mentoring other team members, reviewing verification collateral, and supporting client-facing technical discussions when needed.

Qualifications

• AI experience or interest in learning AI for verification.
• Strong RTL Design and Functional Verification skills, including experience with SystemVerilog and UVM.
• Proficiency in Debugging and Validation of complex digital designs using simulation and related tools.
• Understanding of Good Manufacturing Practice (GMP) or similar quality and process compliance frameworks, where applicable.
• Experience with EDA tools (simulators, waveform viewers, coverage tools) and version control systems.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Ability to work effectively in a remote, distributed team, with clear written and verbal communication skills.
• Familiarity with scripting (e.g., Python, Perl, or shell) to automate verification workflows is beneficial.
• Background in ASIC/SoC design flows and knowledge of standard bus protocols (e.g., AXI, PCIe) is a plus.