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Job summary
An innovative startup at the forefront of AI and semiconductor design is seeking a Design Verification Engineer with expertise in UVM. This role offers the opportunity to work on cutting-edge technologies that automate chip development using AI. As part of a small, elite team, you will develop and deploy UVM testbenches, collaborating closely with machine learning and software engineers. This position is perfect for those eager to explore AI-integrated semiconductor design and make a significant impact in the industry. Join a mission-driven team that is reshaping the future of chip verification and development.
Qualifications
Proven ability to architect UVM environments and debug simulations.
Deep knowledge of verification strategies and coverage-driven development.
Practical experience with EDA tools and proficiency in scripting.
Responsibilities
Build and optimize UVM-based testbenches integrated with AI workflows.
Collaborate with ML and software teams to improve verification artifacts.
Support verification best practices and engage with customer projects.
Skills
UVM
EDA tools
VLSI front-end design
Python scripting
Verification strategies
Constrained-random testing
Communication skills
Education
Bachelor’s degree in Electrical Engineering
Master’s degree in Electrical Engineering
Tools
Synopsys
Cadence
Siemens
Job description
An innovative startup at the forefront of AI and semiconductor design is seeking a Design Verification Engineer with expertise in UVM. This role offers the opportunity to work on cutting-edge technologies that automate chip development using AI. As part of a small, elite team, you will develop and deploy UVM testbenches, collaborating closely with machine learning and software engineers. This position is perfect for those eager to explore AI-integrated semiconductor design and make a significant impact in the industry. Join a mission-driven team that is reshaping the future of chip verification and development.