Principal Verification Engineer

Cypress HCM; San Jose (CA); Hybrid; USD 200,000 - 240,000; Full time

Job summary

A leading company is seeking a Principal Verification Engineer in San Jose, CA. This role involves leading verification engineering efforts for memory integrated circuits, mentoring junior engineers, and collaborating in a dynamic R&D environment. The position offers a competitive salary and benefits, including bonuses and stock options.

Benefits

Medical insurance

Vision insurance

401(k) with company match

Employee stock purchase plan

Relocation assistance

Qualifications

• 7+ years of experience in verification engineering for memory integrated circuits.
• Hands-on experience with DDR memory interfaces.

Responsibilities

• Serve as a technical lead in verification engineering.
• Define verification plans and achieve code coverage goals.

Skills

Verification Engineering

Coding

Scripting

Tools

SystemVerilog

Verilog

UVM

Job description

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This range is provided by Cypress HCM. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$200,000.00/yr - $240,000.00/yr

Additional compensation types

Annual Bonus and RSUs

Principal Verification Engineer

Location: San Jose, CA 95134 or Morrisville, NC 27560

Hybrid Remote: 3 days in the office per week | Reporting To: Director, Design Engineering

Responsibilities:

• Serving as a technical lead with a focus on full chip and/or blocks-level verification engineering
• Collaborating with inventors, engineers, and many others in a dynamic R&D environment
• Mentoring junior team members as needed on verification engineering best practices
• Defining verification plans in collaboration with architects, logic, and mixed signal designers
• Working to achieve code coverage goals and ensuring thoroughly verified designs
• Implementing testbenches, monitors, and scoreboards using the UVM methodology
• Working closely with the lab and systems teams for test plans, silicon bring up, and debugging

Requirements:

• 7+ years of professional experience in verification engineering for memory integrated circuits
• Hands-on experience with DDR memory interfaces, including DDR PHY (DDR4 PHY, DDR5 PHY)
• Experience with UVM methodology and coding in SystemVerilog or Verilog
• Experience with standard ASIC verification flow and software tools
• Experience with mixed-signal integrated circuits (IC)
• Strong coding and scripting skills in Linux/Unix environments
• Experience leading technical solutions across organizations
• Competitive medical, dental, vision, and life insurance plans – including HSA and FSA options
• 401K plan with company match
• Employee stock purchase plan (15% discount)
• Relocation assistance

Compensation:

• $200K - $240K + Bonus + RSUs

Seniority level

• Seniority level

  Director

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering, Information Technology, and Design

• Industries

  Semiconductor Manufacturing and Computer Hardware Manufacturing

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Inferred from the description for this job

Medical insurance

Vision insurance

401(k)

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