Lead Design Verification Engineer (DDR)

SBT; San Francisco (CA); On-site; USD 104,000 - 291,000; Full time

Job summary

A leading executive recruiting firm is seeking a hands-on technical DV lead for a confidential client in the semiconductor industry. The role involves collaborating with HW engineers and SW architects to develop cutting-edge computing systems, ensuring thorough testing and validation of designs. Candidates should have a technical degree and extensive experience in verification methodologies and DDR technologies.

Qualifications

• 5-10+ years of relevant industry experience.
• Expertise in DDR, with a preference for DDR4/DDR5.

Responsibilities

• Develop verification plans and strategies for semiconductor designs.
• Define and develop verification infrastructure for ASIC and FPGA platforms.

Skills

Verification Planning

Verification Methodologies

Collaboration

Education

Technical degree in related engineering field

Tools

SystemVerilog

UVM

Job description

42 minutes ago Be among the first 25 applicants

President at SBT | 19 years of advising leaders in the semiconductor industry and architecting teams from startups to F500 companies

SBT is the exclusive executive recruiting firm for this confidential position.

This confidential company is strategically bringing on a hands-on technical DV lead. In this role, the verification expert will be collaborating cross-functionally with a talented team of systems HW engineers and SW architects in developing cutting-edge computing systems. This individual will have first-hand involvement in the full lifecycle of complex chip development, solving complex challenges directly affecting tier-one customers.

Technical Responsibilities

Verification Planning and Strategy

• Develop verification plans and strategies based on design specifications and requirements to ensure thorough testing and validation of semiconductor designs
• Create verification methodologies, test benches, and test cases to effectively verify and validate digital designs, including RTL (Register Transfer Level) designs

Building DV infrastructure

• Define and develop a comprehensive suite of verification infrastructure and tests that can be leveraged across both ASIC and FPGA platforms
• Collaborate with cross-functional teams to ensure that verification infrastructure and tests are aligned with design requirements and can be effectively used to validate designs

Qualifications

• Technical degree in related engineering field
• 5-10+ years of relevant industry experience
• Expertise in DDR, with a preference for DDR4/DDR5
• Proficiency in verification languages and methodologies, such as SystemVerilog, UVM
• Expertise in network switching data paths related technology is required

Relevant company backgrounds include: AMD, Marvell, Cisco, Broadcom, Intel, Qualcomm, and other networking companies

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering, Manufacturing, and Product Management

• Industries

  Semiconductor Manufacturing, Appliances, Electrical, and Electronics Manufacturing, and Computers and Electronics Manufacturing

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