Principal Design Verification Engineer

Marvell Technology; Santa Clara (CA); On-site; USD 146,000 - 220,000; Full time

Job summary

An innovative firm is seeking a Principal Design Verification Engineer to join their dynamic team. In this role, you will verify complex System-On-Chip designs, develop advanced verification environments, and collaborate with talented engineers to drive impactful projects. This position offers a unique opportunity to work with cutting-edge technology in the data infrastructure domain, contributing to the next generation of enterprise solutions. If you are passionate about solving challenging technical problems and want to make a difference in the semiconductor industry, this is the perfect opportunity for you.

Benefits

Flexible time off

401k

Health and financial wellbeing programs

Equity options

Qualifications

• 10-15 years of experience in design verification or 5-10 years with a Master's/PhD.
• Experience with constrained-random verification environments.

Responsibilities

• Verifying complex SoCs through simulation of RTL and gate level designs.
• Developing verification test environments using SystemVerilog and UVM.

Skills

SystemVerilog

UVM

C Programming

Perl

Python

Shell Scripting

Networking

Storage

Education

Bachelor's degree in Computer Science or Electrical Engineering

Master's/PhD in related fields

Tools

Industry standard verification tools

Job description

Join to apply for the Principal Design Verification Engineer role at Marvell Technology.

Get AI-powered advice on this job and more exclusive features.

Direct message the job poster from Marvell Technology.

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. Marvell addresses the surge of the data economy, providing critical infrastructure from the cloud to the edge. Our Prestera and Teralynx switches offer bandwidth scale for various applications with advanced packet processing and analytics.

Responsibilities

• Verifying blocks or sub-blocks of complex SoCs through simulation of RTL and gate level designs using industry standard tools and processes.
• Developing constrained-random verification test environments using SystemVerilog, UVM, and C programming, including testbenches, checkers, monitors, drivers, and other components.
• Collaborating closely with design and verification engineers to develop and implement verification test plans, schedules, and project deliverables.
• Managing, debugging tests, and regression failures.
• Maintaining and improving existing functional verification infrastructure and methodologies.

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 10-15 years of experience; or Master’s/PhD with 5-10 years of experience.
• Experience with constrained-random verification environments using SystemVerilog and UVM.
• Highly motivated and skilled at solving difficult technical problems.
• Experience with scripting in Perl/Python/Shell.
• Networking, Storage, and/or block/sub-block level experience is a plus.

Compensation

Expected base pay range: $146,850 - $220,000 per annum. Final salary will depend on skills, experience, and location. Additional benefits include bonus, equity, health and financial wellbeing programs, flexible time off, 401k, and more.

Additional Information

Marvell is an equal opportunity employer. Applicants requiring accommodations during the process should contact [e-mail].