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Principal Design Verification Engineer

Marvell Semiconductor, Inc.

California, Santa Clara (MO, CA)

On-site

USD 146,000 - 220,000

Full time

6 days ago
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Job summary

An innovative firm is seeking a skilled verification engineer to join their dynamic team. This role involves verifying complex System-On-Chip designs and developing advanced test environments using SystemVerilog and UVM. You will collaborate closely with design engineers to implement verification plans and enhance existing methodologies. With a focus on solving challenging technical problems, this position offers a unique opportunity to contribute to cutting-edge semiconductor solutions that power data infrastructure globally. Join a company that values your expertise and provides a comprehensive compensation package, including flexible time off and professional growth opportunities.

Benefits

Flexible time off
401(k)
Year-end shutdown
Floating holidays
Paid time off to volunteer

Qualifications

  • 10-15 years of experience in verification of SoCs.
  • Experience with developing test environments using SystemVerilog and UVM.

Responsibilities

  • Verifying complex SoCs through simulation of RTL and gate-level designs.
  • Developing constrained-random verification test environments.

Skills

SystemVerilog
UVM
C programming
Perl
Python
Shell scripting
Networking
Storage

Education

Bachelor's degree in Computer Science
Master's degree in Electrical Engineering
PhD in related fields

Tools

RTL simulation tools

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. Marvell addresses the surge of the data economy, with data centers providing critical infrastructure from the cloud to the edge. Marvell Prestera and Teralynx switches offer the bandwidth scale for every application, with advanced packet processing and analytics to meet demanding needs.

What You Can Expect

  • Verifying blocks or sub-blocks of complex SoCs through simulation of RTL and gate-level designs using industry-standard tools and processes.
  • Developing constrained-random verification test environments using SystemVerilog, UVM, and C programming, including testbenches, checkers, monitors, drivers, and other test components.
  • Collaborating closely with design and verification engineers to develop and implement verification plans, schedules, and deliverables.
  • Managing, debugging tests, and regression failures.
  • Maintaining and improving existing functional verification infrastructure and methodology.

What We're Looking For

  • Bachelor's degree in Computer Science, Electrical Engineering, or related fields with 10-15 years of professional experience; or a Master's degree and/or PhD with 5-10 years of experience.
  • Experience with constrained-random verification test environments using SystemVerilog and UVM.
  • Highly motivated and skilled at solving difficult technical problems.
  • Experience with scripting in Perl, Python, or Shell.
  • Networking, Storage, and/or block/sub-block level experience is a plus.

Expected Base Pay Range (USD)

146,850 - 220,000 per annum. The starting salary will be determined based on skills, experience, qualifications, work location, and market conditions. The pay range may be adjusted according to market conditions.

Additional Compensation and Benefits

We offer a comprehensive total compensation package including base salary, bonus, and equity. Benefits include health and financial wellbeing programs, flexible time off, 401(k), year-end shutdown, floating holidays, and paid time off to volunteer. For questions about our benefits, please ask your recruiter during the interview process.

All qualified applicants will receive consideration regardless of race, color, religion, sex, national origin, sexual orientation, gender identity, disability, or protected veteran status.

Applicants requiring reasonable accommodations during the process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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