Principal SIPI Architect: Chiplet & 2.5D/3D Packaging

Astera Labs; San Jose (CA); On-site; USD 203,000 - 240,000; Full time

Job summary

Astera Labs is seeking a Principal Package Signal & Power Integrity Engineer to architect, optimize, and sign off SIPI solutions for next‑gen connectivity products. You will lead SIPI strategy across PCIe, CXL, Ethernet, and die‑to‑die interconnect, partnering with silicon, package design, PCB, and OSAT teams to balance performance, cost, and manufacturability.

You will drive modeling standards, correlation with lab measurements, and co-design frameworks for multi-die systems, while mentoring

Qualifications

• 10+ years in signal and power integrity for high-performance semiconductors.
• Expert in SIPI modeling and sign-off across chip–package–board.
• Experience with high-speed SerDes, PCIe, CXL, and interposer packaging.

Responsibilities

• Define package SIPI architecture and design strategy for PCIe, CXL, Ethernet, SerDes, and die-to-die interconnect.
• Perform package and system-level SI/PI simulations to develop and sign off models.
• Lead cross-functional execution across silicon, package, PCB, validation, and OSAT partners.
• Drive simulation-to-measurement correlation with lab validation and model accuracy.
• Own SIPI simulation and signoff for 2.5D/3D platforms and chiplet-based packages.
• Define routing guidelines for high-speed SerDes and D2D interfaces; ensure reliability.

Skills

SIPI modeling

SI/PI design

PCIe/CXL SerDes

2.5D/3D packaging

Vendor management

Leadership

Oscilloscope/EM tools

Tools

HFSS

SIwave

Keysight ADS

Q3D

Cadence Sigrity

3D Layout

Job description

Astera Labs is seeking a Principal Package Signal & Power Integrity Engineer to architect, optimize, and sign off SIPI solutions for next‑gen connectivity products. You will lead SIPI strategy across PCIe, CXL, Ethernet, and die‑to‑die interconnect, partnering with silicon, package design, PCB, and OSAT teams to balance performance, cost, and manufacturability.

You will drive modeling standards, correlation with lab measurements, and co-design frameworks for multi-die systems, while mentoring