Principal SerDes Architect for AI Interconnects

Celero Communications, Inc.; EE. UU.; A distancia; USD 200.000 - 300.000; Jornada completa

Descripción de la vacante

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead architecture and design of SerDes for next-generation transceivers powering AI, data center interconnects, and high-speed compute fabrics.

You will shape roadmaps, select topologies, and drive architecture decisions with cross-functional teams. Responsibilities include defining block-level specifications, conducting system-level modeling with MATLAB and SystemVerilog, designing high-performance analog/mixed-signal

Formación

• Master's degree and/or PhD in Electrical Engineering or related field with 10+ years of SerDes experience.
• Proven track record delivering high-speed SerDes from design to tape-out and volume production.
• Experience in lab bring-up, characterization, and debugging for production-ready designs.
• Experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm).

Responsabilidades

• Define architecture, specifications, and topologies for next-generation SerDes.
• Oversee system-level modelling with MATLAB and SystemVerilog to analyze link budgets and jitter budgeting.
• Design high-performance analog/mixed-signal circuits in advanced node technologies.
• Develop and oversee designs of RX/TX equalization (CTLE, DFE), high-speed PLLs, phase interpolators, DLLs, TDCs.
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area.
• Oversee physical layout to minimize parasitics and process variation impacts.
• Analyze Signal Integrity and Power Integrity to meet system-defined targets.
• Lead lab validation, debugging and characterization of SerDes IPs in the lab.
• Correlate silicon measurements with simulated data and drive system optimization.

Educación

Master's degree and/or PhD in Electrical Engineering or related fields

Descripción del empleo

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead architecture and design of SerDes for next-generation transceivers powering AI, data center interconnects, and high-speed compute fabrics.

You will shape roadmaps, select topologies, and drive architecture decisions with cross-functional teams. Responsibilities include defining block-level specifications, conducting system-level modeling with MATLAB and SystemVerilog, designing high-performance analog/mixed-signal