Principal RTL Engineer, IO & Memory for AI Scale

Precision Labs; Town of Texas (WI); Hybrid; USD 180,000 - 255,000; Full time

Benefits offered by this job

Equity

Health insurance

Well-being programs

Job summary

SambaNova Systems seeks a Principal Engineer to own the design, integration, and implementation of high‑speed IO and memory subsystems within the DataScale platform. This hands‑on role requires deep protocol and RTL expertise and a track record of delivering reliable, high‑performance AI systems at scale.

You will drive architecture exploration, microarchitecture, and RTL for IO/memory subsystems, collaborating with software/firmware teams and integrating internal and third‑party IP across the

Qualifications

• MS in Electrical Engineering, Computer Science or related field.
• 7+ years of experience in ASIC design.
• Experience with SystemVerilog RTL design and functional verification.

Responsibilities

• Define IO and memory subsystem direction with system/chip architects.
• Meet PPA constraints through design trade‑offs and feasibility studies.
• Own microarchitecture definition and specification for IO/memory subsystems.

Skills

SystemVerilog RTL

ASIC design

IO and memory subsystems

Power/Performance/Area optimization

AXI/PCIe/Ethernet/UCIe

HBM/CXL memory subsystems

IP vendor evaluation

communication skills

Education

MS in Electrical Engineering or Computer Science

Job description

SambaNova Systems seeks a Principal Engineer to own the design, integration, and implementation of high‑speed IO and memory subsystems within the DataScale platform. This hands‑on role requires deep protocol and RTL expertise and a track record of delivering reliable, high‑performance AI systems at scale.

You will drive architecture exploration, microarchitecture, and RTL for IO/memory subsystems, collaborating with software/firmware teams and integrating internal and third‑party IP across the