Principal RTL Design Engineer, IO & Memory Systems

Precision Labs; Town of Texas (WI); Hybrid; USD 180,000 - 255,000; Full time

Benefits offered by this job

Equity

Health insurance

Well-being programs

Job summary

SambaNova Systems seeks a Principal Engineer to own the design, integration, and implementation of high‑speed IO and memory subsystems within the DataScale platform. This hands‑on role requires deep protocol and RTL expertise and a track record of delivering reliable, high‑performance AI systems at scale.

You will drive architecture exploration, microarchitecture, and RTL for IO/memory subsystems, collaborating with software/firmware teams and integrating internal and third‑party IP across the

Qualifications

• MS in Electrical Engineering, Computer Science or related field.
• 7+ years of experience in ASIC design.
• Experience with SystemVerilog RTL design and functional verification.

Responsibilities

• Define IO and memory subsystem direction with system/chip architects.
• Meet PPA constraints through design trade‑offs and feasibility studies.
• Own microarchitecture definition and specification for IO/memory subsystems.

Skills

SystemVerilog RTL

ASIC design

IO and memory subsystems

Power/Performance/Area optimization

AXI/PCIe/Ethernet/UCIe

HBM/CXL memory subsystems

IP vendor evaluation

communication skills

Education

MS in Electrical Engineering or Computer Science

Job description

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the‑art models with better performance, greater energy efficiency, and faster time to value.

About the role

SambaNova is seeking a Principal Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale® platform. This role is central to delivering reliable, high-performance AI systems at scale.

You will drive these subsystems across the full product lifecycle, from architecture exploration and microarchitecture definition through RTL and integration of internal and third‑party IP (PCIe, Ethernet , CXL, HBM, die‑to‑die). This is a hands‑on role for an engineer with deep protocol and RTL expertise, who can operate in ambiguity and execute with high ownership.

Responsibilities

• Engage in architecture exploration with system and chip architects to define IO and memory subsystem direction
• Drive feasibility studies and design trade‑off analysis to meet PPA constraints
• Own microarchitecture definition and specification for IO and memory subsystems
• Deliver synthesizable, high‑quality SystemVerilog RTL for assigned blocks against functionality, performance, and power targets
• Run the front‑end design flow end to end, covering lint, CDC/RDC, synthesis, timing constraint development, and design‑for‑test readiness
• Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes
• Work closely with verification and emulation teams to ensure design validation coverage and quality
• Collaborate with software and firmware teams to ensure optimal end‑to‑end solutions
• Drive cross‑functional triage of complex functional and performance issues to root cause and closure
• Apply engineering best practices including code review, testing, and refactoring
• Improve design and integration methodology, reuse, and flow scalability

Required Qualifications

• MS in Electrical Engineering, Computer Science, or a related field
• 7+ years of experience in ASIC design
• Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, and functional verification
• Experience with power, performance, or area optimization
• Experience with two or more on‑chip or chip‑to‑chip protocols and interfaces such as AXI, APB, PCIe, Ethernet, or UCIe
• Experience with memory subsystems such as HBM and CXL
• Ability to evaluate and select vendor IP, and to read and distill complex IP and protocol specifications into actionable design requirements
• Clear and effective communicator with a proactive, collaborative approach to problem‑solving

Preferred Qualifications

• Experience taking one or more ASIC products from concept to silicon
• Familiarity with emerging scale‑up protocols (ESUN, SUE, UAL) and scale‑out protocols such as Ultra Ethernet
• Experience designing on‑chip interconnect and traffic‑management logic, including NoC fabrics, switches, arbiters, and quality‑of‑service or congestion control mechanisms
• Knowledge of machine learning and hardware accelerator architectures

Base Salary Range:

Base Pay Range

$180,000 — $255,000 USD

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US‑Based, Full‑Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well‑being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.