Principal RTL Design Engineer — IO & Memory for AI Hardware

SambaNova; Austin (TX); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Equity

Health insurance

Headspace subscription

Job summary

SambaNova is seeking a Principal Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale platform. You will drive the subsystems through architecture to RTL, collaborating with hardware and software teams to deliver scalable AI systems.

This hands-on role requires deep protocol and RTL expertise, ownership mindset, and ability to operate in ambiguity while ensuring performance, power, and reliability targets are met.

Qualifications

• MS in Electrical Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC design.
• Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, and functional verification.
• Experience with power, performance, or area optimization.
• Experience with two or more on-chip or chip-to-chip protocols and interfaces such as AXI, APB, PCIe, Ethernet, or UCIe.
• Experience with memory subsystems such as HBM and CXL.
• Ability to evaluate and select vendor IP, and to read and distill complex IP and protocol specifications into actionable design requirements.
• Clear and effective communicator with a proactive, collaborative approach to problem-solving.

Responsibilities

• Engage in architecture exploration with system and chip architects to define IO and memory subsystem direction.
• Drive feasibility studies and design trade-off analysis to meet PPA constraints.
• Own microarchitecture definition and specification for IO and memory subsystems.
• Deliver synthesizable, high-quality SystemVerilog RTL for assigned blocks against functionality, performance, and power targets.
• Run the front-end design flow end to end, covering lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness.
• Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes.
• Work closely with verification and emulation teams to ensure design validation coverage and quality.
• Collaborate with software and firmware teams to ensure optimal end-to-end solutions.
• Drive cross-functional triage of complex functional and performance issues to root cause and closure.
• Apply engineering best practices including code review, testing, and refactoring.
• Improve design and integration methodology, reuse, and flow scalability.

Skills

Communication

Leading cross-functional teams

Problem-solving

Collaborative approach

Ownership

Education

MS in Electrical Engineering, Computer Science, or related

Tools

SystemVerilog RTL

PCIe

HBM

CXL

AXI/APB/UCIe

Job description

SambaNova is seeking a Principal Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale platform. You will drive the subsystems through architecture to RTL, collaborating with hardware and software teams to deliver scalable AI systems.

This hands-on role requires deep protocol and RTL expertise, ownership mindset, and ability to operate in ambiguity while ensuring performance, power, and reliability targets are met.