Principal RTL Design Engineer – IO & Memory Systems (Equity)

SambaNova; San Jose (CA); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Health insurance

Equity

Well-being benefits

Job summary

SambaNova Systems seeks a Principal Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale platform. This role centers on delivering reliable, high-performance AI systems at scale.

You will drive subsystems across the full product lifecycle—from architecture exploration and microarchitecture definition through RTL and integration of PCIe, Ethernet, CXL, and memory interfaces—collaborating with software and firmware teams to ensure

Qualifications

• MS in Electrical Engineering, Computer Science, or a related field.
• 7+ years of ASIC design experience.
• Proficiency with SystemVerilog RTL design and functional verification.
• Experience with power, performance, or area optimization.
• Experience with AXI, APB, PCIe, Ethernet, or UCIe protocols.
• Experience with memory subsystems such as HBM and/or CXL.
• Ability to distill complex IP/protocol specs into design requirements.

Responsibilities

• Engage in architecture exploration with system and chip architects to define IO and memory subsystem direction.
• Drive feasibility studies and design trade-off analysis to meet PPA constraints.
• Own microarchitecture definition and specification for IO and memory subsystems.
• Deliver synthesizable, high-quality SystemVerilog RTL for assigned blocks against functionality, performance, and power targets.
• Run the front-end design flow end to end, covering lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness.
• Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes.
• Work closely with verification and emulation teams to ensure design validation coverage and quality.
• Collaborate with software and firmware teams to ensure optimal end-to-end solutions.
• Drive cross-functional triage of complex functional and performance issues to root cause and closure.
• Apply engineering best practices including code review, testing, and refactoring.
• Improve design and integration methodology, reuse, and flow scalability.

Skills

ASIC design

SystemVerilog RTL

Power/Perf/Area optimization

AXI/PCIe/Ethernet/UCIe

HBM/CXL memory subsystems

Vendor IP evaluation

Strong communicator

Education

MS in Electrical Engineering or Computer Science

Tools

SystemVerilog RTL

HDL design

Chip interfaces (PCIe, AXI)

Job description

SambaNova Systems seeks a Principal Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale platform. This role centers on delivering reliable, high-performance AI systems at scale.

You will drive subsystems across the full product lifecycle—from architecture exploration and microarchitecture definition through RTL and integration of PCIe, Ethernet, CXL, and memory interfaces—collaborating with software and firmware teams to ensure