Principal PLL Design Engineer: High-Speed Transceivers

Celero Communications, Inc.; United States; Remote; USD 200,000 - 300,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal PLL Design Engineer to lead the architecture and design of high-speed PLLs for next‑gen optical transceivers and SerDes systems.

You will work on advanced node technologies and validate layouts, bringing up PLLs in the lab. The role requires a strong background in PLLs, VCOs, and phase noise, with 5+ years of relevant production experience and proficiency in Cadence Virtuoso, HFSS, and MATLAB.

Qualifications

• Master's degree or PhD in Electrical Engineering or related field.
• 5+ years of PLL design experience with production tape-out exposure.
• Experience with advanced node processes (e.g., 16nm/12nm to 2nm).

Responsibilities

• Understand trade-offs between PLL topologies to meet power, area, jitter, and range requirements.
• Architect, design and simulate analog/mixed-signal PLL blocks (VCOs, charge pumps, dividers, PFDs, loop filters) at transistor level.
• Supervise and verify layouts for floorplanning, matching, and parasitics minimization.

Skills

PLL design

VCO design

Phase noise analysis

High-speed SerDes

Signal integrity

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Virtuoso

EMX/HFSS

MATLAB

Job description

Celero Communications, Inc. is seeking a Principal PLL Design Engineer to lead the architecture and design of high-speed PLLs for next‑gen optical transceivers and SerDes systems.

You will work on advanced node technologies and validate layouts, bringing up PLLs in the lab. The role requires a strong background in PLLs, VCOs, and phase noise, with 5+ years of relevant production experience and proficiency in Cadence Virtuoso, HFSS, and MATLAB.