Principal PLL Design Engineer

Celero Communications, Inc.; United States; Teletrabalho; USD 200 000 - 300 000; Tempo integral

Resumo da oferta

Celero Communications, Inc. is seeking a Principal PLL Design Engineer to lead the architecture and design of high-speed PLLs for next‑gen optical transceivers and SerDes systems.

You will work on advanced node technologies and validate layouts, bringing up PLLs in the lab. The role requires a strong background in PLLs, VCOs, and phase noise, with 5+ years of relevant production experience and proficiency in Cadence Virtuoso, HFSS, and MATLAB.

Qualificações

• Master's degree or PhD in Electrical Engineering or related field.
• 5+ years of PLL design experience with production tape-out exposure.
• Experience with advanced node processes (e.g., 16nm/12nm to 2nm).

Responsabilidades

• Understand trade-offs between PLL topologies to meet power, area, jitter, and range requirements.
• Architect, design and simulate analog/mixed-signal PLL blocks (VCOs, charge pumps, dividers, PFDs, loop filters) at transistor level.
• Supervise and verify layouts for floorplanning, matching, and parasitics minimization.

Conhecimentos

PLL design

VCO design

Phase noise analysis

High-speed SerDes

Signal integrity

Formação académica

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Ferramentas

Cadence Virtuoso

EMX/HFSS

MATLAB

Descrição da oferta de emprego

Principal PLL Design Engineer

About the job

Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.

What You Will Do

• Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range


• Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre


• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization


• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies


• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the‑art lab equipment


• Conduct comprehensive system‑level simulations and validation for PLL integration into advanced transceiver technologies

What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape‑out experience.


• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)


• Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs


• Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system‑level modelling


• Strong communication and documentation skills

Annual Base Salary Range

$200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

Javier Leon
Talent Acquisition
619-227-3193 cell/text
[e-mail]
www.celero.inc