Lead PLL Design Architect for High-Speed Transceivers

Celero Communications, Inc.; Irvine (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal PLL Design Engineer to lead the clocking subsystem for next-generation high-speed interconnects.

You will architect and implement PLLs for transceivers, collaborating with mixed-signal teams to achieve stringent jitter and phase-noise targets. The role requires a Master’s or PhD in Electrical Engineering with 5+ years of PLL design and hands-on experience across 16nm–2nm nodes, VCO design, and tape-out readiness.

Qualifications

• Master’s degree or PhD in Electrical Engineering and 5+ years of PLL design.
• Tape-out experience in production-level processes.
• Experience with 16nm/12nm/7nm/5nm/3nm/2nm processes.
• Strong phase noise analysis, VCO design, and supporting PLL circuitry.
• Proficient in Cadence Virtuoso and MATLAB; experience with EM simulators.

Responsibilities

• Understand trade-offs between PLL topologies to meet power, area, jitter, and frequency range.
• Architect, design and simulate analog/mixed-signal PLL blocks at transistor level using Cadence Virtuoso and Spectre.
• Address challenges in advanced node tech such as self-heating, electromigration, and VCO linearization.
• Supervise layouts to ensure floorplanning, matching, and parasitic minimization.
• Be responsible for PLL bring up in the lab, conducting performance characterization.
• Conduct system-level simulations and validation for PLL integration into advanced transceiver technologies.

Skills

PLL design

Phase noise analysis

VCO design

Advanced node tech

Cadence Virtuoso

EM/HFSS

MATLAB

Strong communication

Education

Master's or PhD in Electrical Engineering

Tools

Cadence Virtuoso

EMX/HFSS

MATLAB

Job description

Celero Communications, Inc. is seeking a Principal PLL Design Engineer to lead the clocking subsystem for next-generation high-speed interconnects.

You will architect and implement PLLs for transceivers, collaborating with mixed-signal teams to achieve stringent jitter and phase-noise targets. The role requires a Master’s or PhD in Electrical Engineering with 5+ years of PLL design and hands-on experience across 16nm–2nm nodes, VCO design, and tape-out readiness.