Senior Physical Design Engineer: Place & Route (On‑Site)

Asteralabs; San Jose (CA); On-site; USD 160,000 - 230,000; Full time

Benefits offered by this job

Equity

Comprehensive benefits

Job summary

Asteralabs in San Jose, California, is looking for a Physical Design Engineer (Place & Route) to play a crucial role in the design of connectivity ASICs used globally.

This on-site generalist role demands a strong background in electrical engineering and at least 8 years of experience in complex SoC design. Candidates should be hands-on with synthesis, timing closure, and possess expertise in CAD tools such as Cadence or Synopsys.

The role offers a competitive salary ranging from $160,000 to $230,000, depending on level and experience, plus equity and benefits.

Qualifications

• 8+ years of experience in complex SoC/silicon products.
• Proven expertise in timing signoff and closure.
• Experience working with RTL and hard-macro blocks.

Responsibilities

• Drive blocks from RTL to GDSII.
• Support the design of connectivity ASICs.
• Coordinate closely with various engineering teams.

Skills

Electrical engineering expertise

Synthesis knowledge

Hands-on with timing closure

Experience with CAD tools

Good scripting skills

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

Cadence

Synopsys

SystemVerilog

Job description

Asteralabs in San Jose, California, is looking for a Physical Design Engineer (Place & Route) to play a crucial role in the design of connectivity ASICs used globally.

This on-site generalist role demands a strong background in electrical engineering and at least 8 years of experience in complex SoC design. Candidates should be hands-on with synthesis, timing closure, and possess expertise in CAD tools such as Cadence or Synopsys.

The role offers a competitive salary ranging from $160,000 to $230,000, depending on level and experience, plus equity and benefits.