Senior Principal Physical Design Engineer - On-Site SoC Signoff

Asteralabs; San Jose (CA); On-site; USD 207,000 - 230,000; Full time

Job summary

Astera Labs is seeking a Senior Principal STA Physical Design Engineer to own RTL-to-GDS flows and full-chip signoff for our connectivity ASIC portfolio. This on-site role requires collaboration with RTL, frontend, and verification teams to ensure robust convergence across complex SoCs.

Qualified candidates have 10+ years in PnR/sign-off, Cadence/Synopsys tool proficiency, and strong scripting (Tcl/Python/Perl). California on-site position with competitive USD salary.

Qualifications

• ≥10 years of PnR and sign-off experience on complex SoCs.
• Expertise in timing closure, EM-IR, DRC/LVS across blocks and full-chip.
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).

Responsibilities

• Independently drive PnR from RTL to GDS, ensuring robust signoff on complex SoCs.
• Identify RTL issues early and coordinate with frontend teams.
• Apply custom clocking techniques and high-speed SERDES/DDR IP timing.
• Manage ECO flows using PT DM SA and hyperscale models for big chips.
• Refine SDC constraints and collaborate with design teams on timing budgets.
• Collaborate with design/implementation/verification to achieve convergence.

Job description

Astera Labs is seeking a Senior Principal STA Physical Design Engineer to own RTL-to-GDS flows and full-chip signoff for our connectivity ASIC portfolio. This on-site role requires collaboration with RTL, frontend, and verification teams to ensure robust convergence across complex SoCs.

Qualified candidates have 10+ years in PnR/sign-off, Cadence/Synopsys tool proficiency, and strong scripting (Tcl/Python/Perl). California on-site position with competitive USD salary.