Senior PD Methodology Engineer - AI-Driven Flows

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a skilled physical design engineer to join the PD methodology team, shaping PPA-focused flows for GPUs, CPUs, and SOCs. You’ll collaborate across RTL, synthesis, DFT, foundry and timing teams to push physical design performance at scale.

Ideal candidates have an MS in Electrical/Computer Engineering and at least 7 years of PD experience with strong EDA tool expertise, STA, RC, UPF, and programming in TCL/Python/C++.

Qualifications

• MS in Electrical or Computer Engineering (or equivalent)
• 7+ years of Physical Design experience
• Proven track record of PPA improvement on high performance/low power designs
• Strong routing/placement/post-route optimization skills
• Background in STA, extraction, timing and RC correlation
• Experience with UPF and FSDB/SAIF for power optimization
• Understanding of EM and IR analysis and closure
• Knowledge of synthesis, hierarchical design, pinning and budgeting flows
• Experience with power distribution networks, design for yield and manufacturability, and thermal management
• Proficiency in EDA tools and programming/scripting (TCL, Perl, Python, C++)

Responsibilities

• Develop innovative physical design methodologies for GPU/CPU/SOC with emphasis on PPA and runtime improvement
• Drive tool and methodology improvements with partners to deliver best-in-class PPA solutions
• Apply AI/ML approaches to CAD to improve design performance and productivity

Skills

Physical Design

PPA optimization

EDA tools

Scripting languages

STA/RC timing

Low Power Design

Power/Area optimization

Education

MS in Electrical or Computer Engineering

Tools

Cypress

Job description

NVIDIA is seeking a skilled physical design engineer to join the PD methodology team, shaping PPA-focused flows for GPUs, CPUs, and SOCs. You’ll collaborate across RTL, synthesis, DFT, foundry and timing teams to push physical design performance at scale.

Ideal candidates have an MS in Electrical/Computer Engineering and at least 7 years of PD experience with strong EDA tool expertise, STA, RC, UPF, and programming in TCL/Python/C++.