PCIe Silicon Validation & Debug Engineer — Bring-Up

HCLTech; Sunnyvale (CA); On-site; USD 78,000 - 148,000; Full time

Job summary

HCLTech in Sunnyvale, CA seeks a PCIe Silicon Validation & Debug Engineer to join the Silicon Engineering team. You will validate PCIe IP and SoC interconnects, develop test plans, and drive bring-up and debug across hardware, firmware, and BIOS teams.

This role emphasizes automated testing with Python, C/C++, SystemVerilog/UVM, and robust debugging skills. A background in PCIe Gen3–Gen6, protocol analyzers, and cross‑functional collaboration is required.

Qualifications

• 4+ years of experience in PCIe validation, silicon validation, verification, or silicon bring-up.
• Hands-on experience writing test cases using C, C++, Python, SystemVerilog, or UVM.
• Experience with protocol analyzers such as LeCroy or Keysight.

Responsibilities

• Develop and execute PCIe validation test plans and test cases.
• Debug PCIe protocol, link training, enumeration, and performance issues.
• Perform silicon bring-up and post-silicon validation.
• Automate test execution, regression, and log analysis using Python.
• Collaborate with hardware, firmware, BIOS, and design teams to resolve system-level issues.

Skills

PCIe validation

silicon validation

verification

silicon bring-up

PCIe protocol

C/C++

Python

SystemVerilog/UVM

debugging

Python scripting

Perl scripting

Tcl scripting

protocol analyzers

Tools

Teledyne LeCroy

Keysight

Job description

HCLTech in Sunnyvale, CA seeks a PCIe Silicon Validation & Debug Engineer to join the Silicon Engineering team. You will validate PCIe IP and SoC interconnects, develop test plans, and drive bring-up and debug across hardware, firmware, and BIOS teams.

This role emphasizes automated testing with Python, C/C++, SystemVerilog/UVM, and robust debugging skills. A background in PCIe Gen3–Gen6, protocol analyzers, and cross‑functional collaboration is required.