Principal PCIe Subsystem RTL Architect

TylSemi, Inc.; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

TylSemi, Inc. in San Jose, CA seeks a Principal PCIe Subsystem RTL lead to own the PCIe microarchitecture from PHY to Transaction Layer, guiding integration of PCIe IP and wrapper RTL.

The role requires deep PCIe expertise, multi-clock-domain design skills, and hands-on leadership of RTL teams. You will collaborate with DV, firmware, and physical design teams to ensure timing, power, and scalability for AI/HL Compute silicon.

Qualifications

• 10+ years of digital IC design experience with PCIe subsystem focus
• Experience leading PCIe/IP integration in SoC/chiplet designs
• Strong SystemVerilog RTL skills and production RTL ownership
• Background with UCIe or related die-to-die interfacing is a plus

Responsibilities

• Own the PCIe subsystem microarchitecture from PHY to TL, defining interfaces and boundaries
• Lead integration of third-party PCIe controller and PHY hard IP with wrapper RTL
• Mentor RTL engineers and drive DV verification plans for PCIe subsystem

Skills

PCIe architecture

Digital IC design

SystemVerilog RTL

Multi-clock-domain design

Verilog/VHDL

RTL mentoring

Education

BS/MS in Electrical/Computer Engineering

Tools

SerDes PHY integration

Wrapper RTL development

Job description

TylSemi, Inc. in San Jose, CA seeks a Principal PCIe Subsystem RTL lead to own the PCIe microarchitecture from PHY to Transaction Layer, guiding integration of PCIe IP and wrapper RTL.

The role requires deep PCIe expertise, multi-clock-domain design skills, and hands-on leadership of RTL teams. You will collaborate with DV, firmware, and physical design teams to ensure timing, power, and scalability for AI/HL Compute silicon.