Lead Mixed-Signal RTL Design Engineer for AI Power ICs

TylSemi; San Jose (CA); On-site; USD 175,000 - 350,000; Full time

Job summary

TylSemi in San Jose is seeking a Principal Mixed Signal RTL Design Engineer to lead silicon-level RTL for intelligent power optimization in AI/HPC applications. You will translate control models to high-quality HDL, design DPWM modules, and collaborate with analog teams on loop compensation and sensor effects.

This role requires strong power-management IC experience and a track record in high-performance mixed-signal design.

Qualifications

• Strong mixed-signal background with power circuits and digital control.
• Experience converting control algorithms into synthesizable RTL (Verilog/SystemVerilog).

Responsibilities

• Lead micro-architecture and RTL design for mixed-signal chiplet.
• Architect and implement digital PID/control loops for high-frequency IVRs.
• Translate MATLAB/Simulink controller models into production RTL (Verilog/SystemVerilog).
• Design ADC interface and DPWM blocks.
• Collaborate with analog designers on compensation and sensor design.
• Optimize for area, power, timing, and metastability across PVT corners.
• Support silicon bring-up and lab hardware debugging.

Skills

Mixed-signal design

RTL design

Verilog/SystemVerilog

HDL Coder

PID control

DPWM

Co-simulation

Education

BSEE / MSEE or PhD

Tools

HDL Coder

Job description

TylSemi in San Jose is seeking a Principal Mixed Signal RTL Design Engineer to lead silicon-level RTL for intelligent power optimization in AI/HPC applications. You will translate control models to high-quality HDL, design DPWM modules, and collaborate with analog teams on loop compensation and sensor effects.

This role requires strong power-management IC experience and a track record in high-performance mixed-signal design.