Remote-Ready Principal Mixed-Signal RTL Engineer

TylSemi, Inc.; San Jose (CA); On-site; USD 175,000 - 350,000; Full time

Job summary

TylSemi, Inc. in San Jose, CA is seeking a Principal Mixed Signal RTL Design Engineer to lead micro-architecture and RTL for AI-oriented chiplet power optimization.

You will own toplevel RTL for mixed-signal chips including analog circuits, micro-controllers and digital logic, delivering production-quality RTL and robust verification. The role demands deep expertise in mixed-signal design, digital control, and DPWM/IVR technologies, with 8+ years in power management ICs or high-performance

Qualifications

• Strong mixed-signal background with power circuits and digital control systems.
• Proven experience converting control algorithms into clean, synthesizable RTL (HDL Coder or hand-coded Verilog/SystemVerilog).
• Deep knowledge of digital PID implementation: quantization, sampling effects, delay, fixed-point arithmetic, and limit cycling.
• Familiarity with high-frequency power converter control and digital PWM modulators (DPWM).
• Experience with mixed-signal verification flows (analog-digital co-simulation).
• Understanding of analog effects impacting digital control: loop delay, sensor non-idealities, inductor non-linearities, PDN resonances.
• Proficiency in digital design tools: Synopsys VCS, Verdi, Design Compiler, PrimeTime (Cadence).

Responsibilities

• Lead micro-architecture and RTL design for Mixed-Signal chiplet focused on AI power optimization.
• Architect and implement digital PID / cascade control loops for high-frequency IVRs.
• Develop micro-architecture and RTL for control of mixed-signal circuits.
• Translate MATLAB/Simulink controller models into production-quality RTL (Verilog/SystemVerilog).
• Design and implement ADC interface, DPWM, and collaborate with analog designers on compensation and sensor issues.
• Analyze and optimize area, power, timing, and metastability across PVT corners.
• Support silicon bring-up, debug, and controller on lab hardware.

Skills

Mixed-signal design

Power circuits

Digital control systems

Digital filters

RTL synthesis

HDL Verilog/SystemVerilog

Education

BSEE / MSEE or PhD

Tools

Synopsys VCS

Verdi

Design Compiler

PrimeTime (Cadence)

Job description

TylSemi, Inc. in San Jose, CA is seeking a Principal Mixed Signal RTL Design Engineer to lead micro-architecture and RTL for AI-oriented chiplet power optimization.

You will own toplevel RTL for mixed-signal chips including analog circuits, micro-controllers and digital logic, delivering production-quality RTL and robust verification. The role demands deep expertise in mixed-signal design, digital control, and DPWM/IVR technologies, with 8+ years in power management ICs or high-performance