Lead PCIe Subsystem RTL Architect (Chiplet AI HPC)

TylSemi; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

TylSemi, Inc. is seeking a Principal PCIe Sub-system Front-end RTL lead to own the PCIe microarchitecture across PHY, MAC, and Transaction Layer. You will drive integration of PCIe hard IP, define lane configurations, and oversee the TL pipeline and flow-control architecture.

Lead a team of RTL engineers, collaborate with firmware and DV, and ensure timing closure with PD teams. Hybrid/Remote US roles welcome for qualified candidates.

Qualifications

• Senior IC design experience with PCIe subsystems and RTL ownership.
• Experience integrating PCIe hard IP (controller/PHY) in production SoCs.
• Strong RTL development and review skills in SystemVerilog.
• Exposure to multi-clock domains and clock-domain crossings.

Responsibilities

• Own PCIe subsystem microarchitecture from PHY through Transaction Layer.
• Lead integration of PCIe hard IP and wrapper RTL with chiplet fabric.
• Define lane configurations and ensure operation across modes.
• Drive TL pipeline, TLP handling, and flow-control orchestration.
• Mentor RTL engineers and coordinate with DV and firmware teams.

Skills

PCIe architecture

SystemVerilog RTL

RTL design review

SoC integration

Multi-clock design

UVM/verification

Education

BS/MS in Electrical Engineering

Tools

UVM

Job description

TylSemi, Inc. is seeking a Principal PCIe Sub-system Front-end RTL lead to own the PCIe microarchitecture across PHY, MAC, and Transaction Layer. You will drive integration of PCIe hard IP, define lane configurations, and oversee the TL pipeline and flow-control architecture.

Lead a team of RTL engineers, collaborate with firmware and DV, and ensure timing closure with PD teams. Hybrid/Remote US roles welcome for qualified candidates.