Principal PCIe RTL Design Engineer — Hybrid

Rambus.com; Hillsboro (OR); Hybrid; USD 108,000 - 201,000; Full time

Benefits offered by this job

Hybrid work model

Onsite 3 days per week, remote 2 days

Base salary, bonus, equity

401(k) matching

Employee stock purchase plan

Medical and dental benefits

Time-off program

Gym membership

Job summary

Rambus is seeking a motivated full-time Principal Design engineer to join our PCIe IP design team in Hillsboro, Oregon. The role focuses on architecture, micro-architecture, and hands-on RTL implementation, with collaboration across global teams.

The successful candidate will prototype IPs on cutting-edge FPGAs, support existing IPs, and thrive in a hybrid work environment that combines onsite collaboration with remote work days.

Qualifications

• 8+ years of RTL Design experience.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or equivalent.
• RTL coding in Verilog/SystemVerilog.
• Good English skills and ability to work with an international team.

Responsibilities

• Contribute to architecture and micro-architecture of next generation PCIe IP.
• Implement designs in SystemVerilog.
• Collaborate with verification team to verify IPs.
• Prototype IPs on cutting edge FPGAs.
• Support existing generations of the IPs.

Skills

Verilog

SystemVerilog

RTL Design

English skills

Education

MS in Electrical Engineering or Computer Engineering

PhD in Electrical Engineering or Computer Engineering

Tools

PCIe

CXL

Job description

Rambus is seeking a motivated full-time Principal Design engineer to join our PCIe IP design team in Hillsboro, Oregon. The role focuses on architecture, micro-architecture, and hands-on RTL implementation, with collaboration across global teams.

The successful candidate will prototype IPs on cutting-edge FPGAs, support existing IPs, and thrive in a hybrid work environment that combines onsite collaboration with remote work days.