Lead PCIe Subsystem RTL Architect

TYLsemi; United States; Hybrid; USD 180,000 - 240,000; Full time

Job summary

TylSemi, Inc. is seeking a Principal PCIe Sub-system Front-end RTL lead to own the PCIe microarchitecture for next‑gen chiplet based SoCs aimed at HPC/AI silicon.

You will drive integration of PCIe hard IP, define lane configurations, and own the Transaction Layer pipeline across modes. You will collaborate with firmware for register maps and telemetry, work with the PD team for timing, and mentor RTL engineers while guiding DV with UVM coverage.

Qualifications

• 10+ years in digital IC design with PCIe focus.
• Experience integrating PCIe hard IP in SoCs.
• Strong SystemVerilog RTL skills for pipelined state machines.
• Familiar with PCIe test/certification processes (PCI-SIG).
• BS/MS in EE/CE or equivalent.

Responsibilities

• Own PCIe subsystem microarchitecture from PHY to Transaction Layer.
• Lead integration of third‑party PCIe controller and PHY hard IP with wrapper RTL.
• Define lane configuration and configurations across modes.
• Drive Transaction Layer pipeline, including TLP reception and routing.
• Own Virtual Channel and flow‑control architecture.
• Define PCIe integration interfaces (TLP-to-flit, flow-control mapping, error handling).
• Collaborate on PCIe register map, mode-select interface, telemetry structures.
• Work with Physical Design to meet timing closure for PCIe subsystem.
• Maintain PCIe performance budgets (bandwidth, latency, error recovery).
• Lead bring‑up planning, instrumentation, loopback modes, production hand‑off criteria.
• Mentor RTL engineers and guide DV team on UVM plan and coverage.
• Be technical contact for PCIe customer integration and interoperability.

Skills

PCIe architecture

RTL design

SystemVerilog

Multi-clock-domain

SR‑IOV

IP integration

P&R constraints

Debug instrumentation

Education

BS/MS in Electrical/Computer Engineering

Tools

UVM

Verilog/SystemVerilog

Job description

TylSemi, Inc. is seeking a Principal PCIe Sub-system Front-end RTL lead to own the PCIe microarchitecture for next‑gen chiplet based SoCs aimed at HPC/AI silicon.

You will drive integration of PCIe hard IP, define lane configurations, and own the Transaction Layer pipeline across modes. You will collaborate with firmware for register maps and telemetry, work with the PD team for timing, and mentor RTL engineers while guiding DV with UVM coverage.